Yonggang Yong Li

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Conductive route patterning for electronic substrates
- Patent number 12,027,466
- Issue date Jul 2, 2024
- Intel Corporation
- Jeremy D. Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patternable die attach materials and processes for patterning
- Patent number 11,923,312
- Issue date Mar 5, 2024
- Intel Corporation
- Bai Nie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective deposition of embedded thin-film resistors for semiconduc...
- Patent number 11,728,265
- Issue date Aug 15, 2023
- Intel Corporation
- Brandon C. Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating an RF filter on a semiconductor package using selective...
- Patent number 11,605,867
- Issue date Mar 14, 2023
- Intel Corporation
- Brandon C. Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ component fabrication of a highly efficient, high inductanc...
- Patent number 11,404,389
- Issue date Aug 2, 2022
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate embedded magnetic core inductors and method of making
- Patent number 11,348,718
- Issue date May 31, 2022
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating an RF filter on a semiconductor package using selective...
- Patent number 11,081,768
- Issue date Aug 3, 2021
- Intel Corporation
- Brandon C. Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic package that includes lamination layer
- Patent number 10,985,080
- Issue date Apr 20, 2021
- Intel Corporation
- Pramod Malatkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device package with reduced thickness variation
- Patent number 10,910,327
- Issue date Feb 2, 2021
- Intel Corporation
- Yonggang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin electronic package elements using laser spallation
- Patent number 10,672,701
- Issue date Jun 2, 2020
- Intel Corporation
- Vivek Raghunathan
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Embedded circuit patterning feature selective electroless
- Patent number 10,586,715
- Issue date Mar 10, 2020
- Intel Corporation
- Yonggang Yong Li
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 10,306,760
- Issue date May 28, 2019
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Selective metallization of an integrated circuit (IC) substrate
- Patent number 10,290,557
- Issue date May 14, 2019
- Intel Corporation
- Brandon C. Marin
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for forming a semiconductor device substrate
- Patent number 9,820,390
- Issue date Nov 14, 2017
- Intel Corporation
- Mihir K. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip integration with through silicon via (TSV) die embedded i...
- Patent number 9,716,084
- Issue date Jul 25, 2017
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 9,648,733
- Issue date May 9, 2017
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Embedded circuit patterning feature selective electroless copper pl...
- Patent number 9,646,854
- Issue date May 9, 2017
- Intel Corporation
- Yonggang Yong Li
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Panel with releasable core
- Patent number 9,554,472
- Issue date Jan 24, 2017
- Intel Corporation
- Ching-Ping Janet Shen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Spaced configuration of acousto-optic deflectors for laser beam sca...
- Patent number 9,442,286
- Issue date Sep 13, 2016
- Intel Corporation
- Yonggang Li
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multichip integration with through silicon via (TSV) die embedded i...
- Patent number 9,397,079
- Issue date Jul 19, 2016
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Same layer microelectronic circuit patterning using hybrid laser pr...
- Patent number 9,113,547
- Issue date Aug 18, 2015
- Intel Corporation
- John Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multichip integration with through silicon via (TSV) die embedded i...
- Patent number 9,000,599
- Issue date Apr 7, 2015
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid core through holes and vias
- Patent number 8,928,151
- Issue date Jan 6, 2015
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a multilayer substrate core structure using seque...
- Patent number 8,877,565
- Issue date Nov 4, 2014
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Hybrid-core through holes and vias
- Patent number 8,552,564
- Issue date Oct 8, 2013
- Intel Corporation
- Mihir K. Roy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and core materials for semiconductor packaging
- Patent number 8,456,016
- Issue date Jun 4, 2013
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 8,440,916
- Issue date May 14, 2013
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Utilizing aperture with phase shift feature in forming microvias
- Patent number 8,318,536
- Issue date Nov 27, 2012
- Intel Corporation
- Yonggang Li
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming micro-vias using a two stage laser drilling process
- Patent number 8,288,682
- Issue date Oct 16, 2012
- Intel Corporation
- Islam Salama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Coaxial plated through holes (PTH) for robust electrical performance
- Patent number 8,227,706
- Issue date Jul 24, 2012
- Intel Corporation
- Mihir Roy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
DRY SEED REMOVAL BY LASER FOR LINE-SPACE AND VIA FORMATION
- Publication number 20240332153
- Publication date Oct 3, 2024
- Intel Corporation
- Tchefor NDUKUM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIRECT ELECTROPLATING ON MODIFIED POLYMER-GRAPHENE COMPOSITES
- Publication number 20240213328
- Publication date Jun 27, 2024
- Intel Corporation
- Vinith BEJUGAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS COATING TO MINIMIZE ROUGHNESS INSIDE THROUGH GLASS VIAS
- Publication number 20240188225
- Publication date Jun 6, 2024
- Intel Corporation
- Vinith BEJUGAM
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
DRY METHOD FOR METAL-DEFINED PAD FORMATION
- Publication number 20240181572
- Publication date Jun 6, 2024
- Intel Corporation
- Tchefor NDUKUM
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES
- Publication number 20240112970
- Publication date Apr 4, 2024
- Intel Corporation
- Hanyu Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARRIER CHUCK AND METHODS OF FORMING AND USING THEREOF
- Publication number 20240096678
- Publication date Mar 21, 2024
- Intel Corporation
- Deniz TURAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING
- Publication number 20240088052
- Publication date Mar 14, 2024
- Intel Corporation
- Bai NIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGN OPTIMIZATION FOR RASTER SCANNING
- Publication number 20230361002
- Publication date Nov 9, 2023
- Intel Corporation
- Vinith BEJUGAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR REMOVING LASER DEBOND RESIDUE FROM SUBSTRATE
- Publication number 20230294204
- Publication date Sep 21, 2023
- Intel Corporation
- Jeremy ECTON
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
MICROELECTRONIC ASSEMBLIES INCLUDING INTERCONNECTS WITH DIFFERENT S...
- Publication number 20230197679
- Publication date Jun 22, 2023
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING
- Publication number 20230146165
- Publication date May 11, 2023
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE FIRST FAN-OUT ARCHITECTURE FOR ELECTRIC AND OPTICAL INTEGRATION
- Publication number 20230090133
- Publication date Mar 23, 2023
- Bai Nie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE LAST AND WAVEGUIDE LAST ARCHITECTURE FOR SILICON PHOTONIC PACKA...
- Publication number 20230087124
- Publication date Mar 23, 2023
- Bai Nie
- G02 - OPTICS
Information Patent Application
GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHIT...
- Publication number 20230085411
- Publication date Mar 16, 2023
- Intel Corporation
- Sameer Paital
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING
- Publication number 20220254559
- Publication date Aug 11, 2022
- Intel Corporation
- Srinivas Venkata Ramanuja Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE ROUTE PATTERNING FOR ELECTRONIC SUBSTRATES
- Publication number 20220093520
- Publication date Mar 24, 2022
- Intel Corporation
- Jeremy D. Ecton
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
FABRICATING AN RF FILTER ON A SEMICONDUCTOR PACKAGE USING SELECTIVE...
- Publication number 20210305668
- Publication date Sep 30, 2021
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATING AN RF FILTER ON A SEMICONDUCTOR PACKAGE USING SELECTIVE...
- Publication number 20200373261
- Publication date Nov 26, 2020
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE PACKAGE WITH REDUCED THICKNESS VARIATION
- Publication number 20200312787
- Publication date Oct 1, 2020
- Intel Corporation
- Yonggang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING
- Publication number 20200312771
- Publication date Oct 1, 2020
- Intel Corporation
- Bai NIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL BASED CERAMIC FILLERS AS CATALYSTS FOR SELECTIVE ELECTROLESS...
- Publication number 20200176272
- Publication date Jun 4, 2020
- Intel Corporation
- Vivek RAGHUNATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-SITU COMPONENT FABRICATION OF A HIGHLY EFFICIENT, HIGH INDUCTANC...
- Publication number 20200105685
- Publication date Apr 2, 2020
- Jeremy ECTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUPPORTS HAVING INDUCTORS WITH MAGNETIC...
- Publication number 20200091053
- Publication date Mar 19, 2020
- Intel Corporation
- Sameer Paital
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE DEPOSITION OF EMBEDDED THIN-FILM RESISTORS FOR SEMICONDUC...
- Publication number 20200083164
- Publication date Mar 12, 2020
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LASER PLANARIZATION WITH IN-SITU SURFACE TOPOGRAPHY CONTROL AND MET...
- Publication number 20200078884
- Publication date Mar 12, 2020
- Intel Corporation
- Bai Nie
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING
- Publication number 20200005987
- Publication date Jan 2, 2020
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURES WITHIN A SUBSTRATE LAYER TO CURE MAGNETIC PASTE
- Publication number 20200005990
- Publication date Jan 2, 2020
- Intel Corporation
- Sameer PAITAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC PACKAGE THAT INCLUDES LAMINATION LAYER
- Publication number 20180350709
- Publication date Dec 6, 2018
- Intel Corporation
- Pramod Malatkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN ELECTRONIC PACKAGE ELEMENTS USING LASER SPALLATION
- Publication number 20180308792
- Publication date Oct 25, 2018
- Vivek Raghunathan
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SELECTIVE METALLIZATION OF AN INTEGRATED CIRCUIT (IC) SUBSTRATE
- Publication number 20180033707
- Publication date Feb 1, 2018
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS

Yonggang Yong Li

Person

Patents Grantslast 30 patents

Conductive route patterning for electronic substrates

Patternable die attach materials and processes for patterning

Selective deposition of embedded thin-film resistors for semiconduc...

Fabricating an RF filter on a semiconductor package using selective...

In-situ component fabrication of a highly efficient, high inductanc...

Substrate embedded magnetic core inductors and method of making

Fabricating an RF filter on a semiconductor package using selective...

Electronic package that includes lamination layer

Electronic device package with reduced thickness variation

Thin electronic package elements using laser spallation

Embedded circuit patterning feature selective electroless

Method of forming a substrate core structure using microvia laser d...

Selective metallization of an integrated circuit (IC) substrate

Process for forming a semiconductor device substrate

Multichip integration with through silicon via (TSV) die embedded i...

Method of forming a substrate core structure using microvia laser d...

Embedded circuit patterning feature selective electroless copper pl...

Panel with releasable core

Spaced configuration of acousto-optic deflectors for laser beam sca...

Multichip integration with through silicon via (TSV) die embedded i...

Same layer microelectronic circuit patterning using hybrid laser pr...

Multichip integration with through silicon via (TSV) die embedded i...

Hybrid core through holes and vias

Method of forming a multilayer substrate core structure using seque...

Hybrid-core through holes and vias

Method and core materials for semiconductor packaging

Method of forming a substrate core structure using microvia laser d...

Utilizing aperture with phase shift feature in forming microvias

Forming micro-vias using a two stage laser drilling process

Coaxial plated through holes (PTH) for robust electrical performance

Patents Applicationslast 30 patents

DRY SEED REMOVAL BY LASER FOR LINE-SPACE AND VIA FORMATION

DIRECT ELECTROPLATING ON MODIFIED POLYMER-GRAPHENE COMPOSITES

GLASS COATING TO MINIMIZE ROUGHNESS INSIDE THROUGH GLASS VIAS

DRY METHOD FOR METAL-DEFINED PAD FORMATION

SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES

CARRIER CHUCK AND METHODS OF FORMING AND USING THEREOF

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

DESIGN OPTIMIZATION FOR RASTER SCANNING

METHOD AND APPARATUS FOR REMOVING LASER DEBOND RESIDUE FROM SUBSTRATE

MICROELECTRONIC ASSEMBLIES INCLUDING INTERCONNECTS WITH DIFFERENT S...

SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING

DIE FIRST FAN-OUT ARCHITECTURE FOR ELECTRIC AND OPTICAL INTEGRATION

DIE LAST AND WAVEGUIDE LAST ARCHITECTURE FOR SILICON PHOTONIC PACKA...

GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHIT...

SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING

CONDUCTIVE ROUTE PATTERNING FOR ELECTRONIC SUBSTRATES

FABRICATING AN RF FILTER ON A SEMICONDUCTOR PACKAGE USING SELECTIVE...

FABRICATING AN RF FILTER ON A SEMICONDUCTOR PACKAGE USING SELECTIVE...

ELECTRONIC DEVICE PACKAGE WITH REDUCED THICKNESS VARIATION

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

METAL BASED CERAMIC FILLERS AS CATALYSTS FOR SELECTIVE ELECTROLESS...

IN-SITU COMPONENT FABRICATION OF A HIGHLY EFFICIENT, HIGH INDUCTANC...

INTEGRATED CIRCUIT PACKAGE SUPPORTS HAVING INDUCTORS WITH MAGNETIC...

SELECTIVE DEPOSITION OF EMBEDDED THIN-FILM RESISTORS FOR SEMICONDUC...

LASER PLANARIZATION WITH IN-SITU SURFACE TOPOGRAPHY CONTROL AND MET...

SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING

STRUCTURES WITHIN A SUBSTRATE LAYER TO CURE MAGNETIC PASTE

ELECTRONIC PACKAGE THAT INCLUDES LAMINATION LAYER

THIN ELECTRONIC PACKAGE ELEMENTS USING LASER SPALLATION

SELECTIVE METALLIZATION OF AN INTEGRATED CIRCUIT (IC) SUBSTRATE