You Chye How

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Taman Semabok Permai, MY

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Patents Grantslast 30 patents

Information Patent Grant
Coated semiconductor dies
- Patent number 11,837,518
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Michael Todd Wyant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leads for leadframe and semiconductor package
- Patent number 11,830,791
- Issue date Nov 28, 2023
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die integrated circuit packages and methods of manufacturing...
- Patent number 11,328,984
- Issue date May 10, 2022
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for making a multilevel leadframe by etching a conductive s...
- Patent number 10,804,114
- Issue date Oct 13, 2020
- Texas Instruments Incorporated
- Lee Han Meng@ Eugene Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package having an IC die between top and bottom...
- Patent number 10,381,293
- Issue date Aug 13, 2019
- Texas Instruments Incorporated
- Lee Han Meng@Eugene Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making lead frames for integrated circuit packages
- Patent number 10,079,162
- Issue date Sep 18, 2018
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making lead frames for integrated circuit packages
- Patent number 9,978,613
- Issue date May 22, 2018
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package fabrication with die attach paddle havin...
- Patent number 9,620,388
- Issue date Apr 11, 2017
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with die attach paddle having at least o...
- Patent number 9,202,778
- Issue date Dec 1, 2015
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated passive flip chip package
- Patent number 9,123,626
- Issue date Sep 1, 2015
- Texas Instruments Incorporated
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for dicing die attach film on a semiconductor...
- Patent number 8,647,966
- Issue date Feb 11, 2014
- National Semiconductor Corporation
- Ken Fei Lim
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Grant
Methods and systems for packaging integrated circuits
- Patent number 8,048,781
- Issue date Nov 1, 2011
- National Semiconductor Corporation
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems of packaging integrated circuits
- Patent number 8,030,138
- Issue date Oct 4, 2011
- National Semiconductor Corporation
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with integrated heat sink
- Patent number 8,018,050
- Issue date Sep 13, 2011
- National Semiconductor Corporation
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low stress cavity package
- Patent number 7,868,433
- Issue date Jan 11, 2011
- National Semiconductor Corporation
- Peng Soon Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems for packaging integrated circuits
- Patent number 7,863,757
- Issue date Jan 4, 2011
- National Semiconductor Corporation
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems for packaging integrated circuits
- Patent number 7,749,809
- Issue date Jul 6, 2010
- National Semiconductor Corporation
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical leadless leadframe package
- Patent number 7,582,954
- Issue date Sep 1, 2009
- National Semiconductor Corporation
- Peng Soon Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Marking semiconductor devices through a mount tape
- Patent number 6,972,244
- Issue date Dec 6, 2005
- National Semiconductor Corporation
- Viraj A. Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
COATED SEMICONDUCTOR DIES
- Publication number 20240055313
- Publication date Feb 15, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Michael Todd WYANT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COATED SEMICONDUCTOR DIES
- Publication number 20220068744
- Publication date Mar 3, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Michael Todd WYANT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADS FOR LEADFRAME AND SEMICONDUCTOR PACKAGE
- Publication number 20200135621
- Publication date Apr 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- YOU CHYE HOW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE INTEGRATED CIRCUIT PACKAGES AND METHODS OF MANUFACTURING...
- Publication number 20190206772
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Making Lead Frames for Integrated Circuit Packages
- Publication number 20180261469
- Publication date Sep 13, 2018
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE
- Publication number 20170213781
- Publication date Jul 27, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Lee Han Meng@Eugene Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE
- Publication number 20170053883
- Publication date Feb 23, 2017
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multilevel Leadframe
- Publication number 20160240390
- Publication date Aug 18, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Lee Han Meng@ Eugene Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE FABRICATION WITH DIE ATTACH PADDLE HAVIN...
- Publication number 20160071743
- Publication date Mar 10, 2016
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE
- Publication number 20150262920
- Publication date Sep 17, 2015
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED PASSIVE FLIP CHIP PACKAGE
- Publication number 20150243639
- Publication date Aug 27, 2015
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multilevel Leadframe
- Publication number 20150108626
- Publication date Apr 23, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Lee Han Meng@ Eugene Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH DIE ATTACH PADDLE HAVING AT LEAST O...
- Publication number 20150054145
- Publication date Feb 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARRIER TAPE
- Publication number 20150053586
- Publication date Feb 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Application
Integrated Circuit with Stress Isolation
- Publication number 20150035130
- Publication date Feb 5, 2015
- TEXAS INSTRUMENTS INCORPORATED
- You Chye How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multilevel Leadframe
- Publication number 20140346656
- Publication date Nov 27, 2014
- Lee Han Meng@ Eugene Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR DICING DIE ATTACH FILM ON A SEMICONDUCTOR...
- Publication number 20120313231
- Publication date Dec 13, 2012
- National Semiconductor Corporation
- Ken Fei LIM
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Application
METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS
- Publication number 20100237487
- Publication date Sep 23, 2010
- National Semiconductor Corporation
- You Chye HOW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW STRESS CAVITY PACKAGE
- Publication number 20100052123
- Publication date Mar 4, 2010
- National Semiconductor Corporation
- Peng Soon LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL LEADLESS LEADFRAME PACKAGE
- Publication number 20090212382
- Publication date Aug 27, 2009
- National Semiconductor Corporation
- Peng Soon LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS
- Publication number 20090189279
- Publication date Jul 30, 2009
- National Semiconductor Corporation
- You Chye HOW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS
- Publication number 20090152707
- Publication date Jun 18, 2009
- National Semiconductor Corporation
- You Chye HOW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK
- Publication number 20090115037
- Publication date May 7, 2009
- National Semiconductor Corporation
- You Chye HOW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH INTEGRAL HEAT SINKS
- Publication number 20080242003
- Publication date Oct 2, 2008
- National Semiconductor Corporation
- You Chye HOW
- H01 - BASIC ELECTRIC ELEMENTS

You Chye How

Person

Patents Grantslast 30 patents

Coated semiconductor dies

Leads for leadframe and semiconductor package

Multi-die integrated circuit packages and methods of manufacturing...

Methods for making a multilevel leadframe by etching a conductive s...

Integrated circuit package having an IC die between top and bottom...

Method for making lead frames for integrated circuit packages

Method for making lead frames for integrated circuit packages

Integrated circuit package fabrication with die attach paddle havin...

Integrated circuit package with die attach paddle having at least o...

Integrated passive flip chip package

Method and apparatus for dicing die attach film on a semiconductor...

Methods and systems for packaging integrated circuits

Methods and systems of packaging integrated circuits

Integrated circuit package with integrated heat sink

Low stress cavity package

Methods and systems for packaging integrated circuits

Methods and systems for packaging integrated circuits

Optical leadless leadframe package

Marking semiconductor devices through a mount tape

Patents Applicationslast 30 patents

COATED SEMICONDUCTOR DIES

COATED SEMICONDUCTOR DIES

LEADS FOR LEADFRAME AND SEMICONDUCTOR PACKAGE

MULTI-DIE INTEGRATED CIRCUIT PACKAGES AND METHODS OF MANUFACTURING...

Method for Making Lead Frames for Integrated Circuit Packages

INTEGRATED CIRCUIT PACKAGE

INTEGRATED CIRCUIT PACKAGE

Multilevel Leadframe

INTEGRATED CIRCUIT PACKAGE FABRICATION WITH DIE ATTACH PADDLE HAVIN...

INTEGRATED CIRCUIT PACKAGE

INTEGRATED PASSIVE FLIP CHIP PACKAGE

Multilevel Leadframe

INTEGRATED CIRCUIT PACKAGE WITH DIE ATTACH PADDLE HAVING AT LEAST O...

CARRIER TAPE

Integrated Circuit with Stress Isolation

Multilevel Leadframe

METHOD AND APPARATUS FOR DICING DIE ATTACH FILM ON A SEMICONDUCTOR...

METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS

LOW STRESS CAVITY PACKAGE

OPTICAL LEADLESS LEADFRAME PACKAGE

METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS

METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS

INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK

INTEGRATED CIRCUIT DEVICES WITH INTEGRAL HEAT SINKS