The present invention generally relates to the packaging of integrated circuit (IC) devices. More particularly, the present invention relates to forming an integral heat sink on the back surface of the die.
There are a number of conventional processes for packaging integrated circuit devices. Many packaging techniques use a lead frame that has been stamped or etched from a metal sheet to provide electrical interconnects to external devices. A die is electrically connected to portions of the lead frame via bonding wires, solder bumps, or other suitable electrical connections. Generally, the die, the lead frame and bonding wires or solder bumps are then encapsulated in a mold while leaving selected portions of the lead frame exposed to facilitate electrical connection to external devices.
Because the IC devices may become hot while in operation, sometimes a heat sink is soldered or glued to the die to help absorb and dissipate heat from the die. Efficient heat sinks are important to IC devices, because faster device cooling rate generally leads to better device performance and stability.
Although existing heat-sinks techniques work well, there are continuing efforts to develop even more efficient designs and methods for dissipating heat for the IC devices.
Broadly speaking, the present invention relates to the formation of an integral heat sink on the back surface of a die. In a separate aspect, a packaging system that connects the die, along with its integral heat sink, to a lead frame via solder bumps or bonding wires is described.
In one embodiment, a wafer level method for forming integral heat sinks on the back surface of IC devices is described. The method comprises depositing a first metallic layer over the back surface of a wafer, depositing a second metallic layer over the first metallic layer, and optionally depositing a third metallic layer over the second metallic layer. The plurality of metallic layers form a heat sink that is integrally formed on the back surface of the wafer. When the wafer is diced into multiple semiconductor devices, each semiconductor device has an integral heat sink that includes the plurality of metallic layers formed on the back surface of the die.
In some preferred embodiments, the first layer of the heat sink is formed by sputtering and the second layer is a substantially thicker mass layer formed at least in part by electroplating. In various implementations, a seed layer of the second metallic material may be deposited by sputtering prior to the electroplating. In some embodiments the first metallic layer may be an adhesion layer formed from a material such as titanium, titanium-tungsten, or nickel-vanadium; the thicker, electroplated second metallic layer may be formed from copper or aluminum. Since both copper and aluminum are susceptible to corrosion, in many applications it is desirable to also provide a non-corrosive (or less corrosive) protective layer formed from a material such as titanium, titanium-tungsten, or nickel-vanadium over the mass layer. The protective layer does not need to be particularly thick and therefore may be formed by sputtering in many applications.
The thicknesses of the various layers may vary widely based on the needs of a particular design. By way of example, thickness under 2000 angstroms are suitable for the adhesive and protective layers. Thickness in the range of approximately 10,000 to 100,000 angstroms work well for the mass layer.
In another embodiment, an integrated circuit (IC) package that incorporates a die having an integral heat sink is described. The IC package comprises a semiconductor device with an integral heat sink that is connected to a lead frame via solder bumps or bonding wires. At least portions of the semiconductor device, the lead frame, and solder bumps or bonding wires are encapsulated in an encapsulant, such as a molding material. The outer layer of the metallic material that forms the integral heat sink is exposed to the environment, thus conducting heat away from the die.
These and other features, aspects, and advantages of the invention will be described in more detail below in the detailed description and in conjunction with the following figures.
For a better understanding of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:
Like reference numerals refer to corresponding parts throughout the drawings.
The present invention generally relates to the packaging of integrated circuit (IC) devices. More specifically, the present invention relates to forming an integral heat sink on the back surface of the die.
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessary obscuring of the present invention.
According to an alternative embodiment, bonding wires may be used to connect each individual IC device to a lead frame during the packaging step. In this case, one end of each bonding wire is thermosonically welded to an associated bond pad and the other end is secured to the lead frame or other suitable structure. The bonding wires are typically formed from gold but may be formed from other conductive materials such as aluminum or copper.
First, a first layer of metallic material is deposited over the back surface of the wafer (step 210 of
This first layer of metallic material 330 helps adhere subsequent layers of metallic materials to the wafer 100. By way of example, metallic materials such as titanium, titanium-tungsten, or nickel-vanadium work well as the adhesion layer. The thickness of the first metallic layer may vary widely based on the needs of a particular application. By way of example, in the described embodiment thicknesses in the range of approximately 100 to 900 ångströms work well. Preferably, the first metallic layer 330 covers the entire back surface of the wafer 100.
Next, a second layer of metallic material is deposited over the first layer of metallic material (step 220 of
Second, a thick layer of the second metallic material 342 is electroplated over the thin layer 341. Together, the thin layer 341 and the thick layer 342 form the second layer of metallic material 340. Platting is a surface-covering technique in which a metal is deposited onto a conductive surface. Platting is more cost-effective than sputtering, and is generally preferred when depositing a thick layer of metallic material. This step is illustrated in
A variety of different materials may be used as the second (mass) layer. By way of example, metallic materials such as copper or aluminum work well as the second layer 340. Preferably, the second metallic layer 340 covers the entire first metallic layer 330.
Next, a third layer of metallic material is deposited over the second layer of metallic material (step 230 of
This third layer of metallic material 350 helps protect the second layer of metallic material 340 from corrosion. By way of example, non-corrosive, or minimally corrosive metallic materials such as titanium, titanium-tungsten, or nickel-vanadium work well as the protective layer. In the described embodiment this third metallic layer has thicknesses in the range of approximately 1,000 to 1,500 ångströms. Preferably, the third metallic layer 350 covers the entire second metallic layer 340.
According to an alternative embodiment, no protective layer is deposited over the mass (second) layer of metallic material. In this case, the second metallic layer is exposed and therefore, depending on the material used, may be susceptible to corrosion. However, in many situations an entity that mounts the described die or package in a larger system may have the ability to readily remove or otherwise handle such corrosion and therefore corrosion may not be a particular concern in some applications.
The first metallic layer 330, the second metallic layer 340, and (when present) the third metallic layer 350 together form an integral heat sink on the back surface of the wafer 100.
After the integral heat sink has been formed, the wafer may be further processed and diced in a conventional manner. In the illustrated embodiment, the wafer is mounted on a mounting tape, such that the active surface of the wafer faces the mounting tape (step 240 of
The wafer may be diced in a variety of manners.
Second, a narrower cut 371 is made completely through the remaining wafer 100. This step is illustrated in
In one embodiment, the described dice with integral heat sinks are used in a flip chip on lead (FLOP) style packages.
In order to facilitate these processes, each device area 404 includes a plurality of leads 408, each supported at one end by the tie bars 406. As illustrated in
First, each semiconductor device is removed from the mounting tape (step 510 of
Next, the semiconductor device is connected to a lead frame (step 520 of
According to an alternative embodiment, bonding wires may be used to electrically connect the individual semiconductor device to the lead frame.
Next, according to one embodiment, at least parts of the semiconductor device, the solder bumps, and the lead frame are encapsulated in an encapsulant, while leaving the surface of the integral heat sink formed by the uppermost metallic layer exposed (step 530 of
Finally, the encapsulated integrated circuit device and the lead frame are singulated into multiple packages (step 540 of
The present invention has several advantages. For example, the integral heat sink formed on the back surface of the die increases the thermal dissipation while the IC device is in operation. In addition, using solder bumps with flip chip packaging increases current carrying capability.
The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. It will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings. For example, the semiconductor device shown in
The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.