Yow Juang W. Liu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits with nonvolatile memory elements
- Patent number 8,467,240
- Issue date Jun 18, 2013
- Altera Corporation
- Albert Ratnakumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element circuitry with stressed transistors
- Patent number 8,218,353
- Issue date Jul 10, 2012
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for adjusting performance of integrated circuits
- Patent number 8,138,786
- Issue date Mar 20, 2012
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with nonvolatile memory elements
- Patent number 8,116,130
- Issue date Feb 14, 2012
- Altera Corporation
- Albert Ratnakumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for electrostatic discharge circuitry with sn...
- Patent number 8,089,744
- Issue date Jan 3, 2012
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device for electrostatic discharge protection
- Patent number 7,981,753
- Issue date Jul 19, 2011
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically-programmable transistor antifuses
- Patent number 7,772,591
- Issue date Aug 10, 2010
- Altera Corporation
- Chih-Ching Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device for electrostatic discharge protection
- Patent number 7,671,416
- Issue date Mar 2, 2010
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection structure
- Patent number 7,638,847
- Issue date Dec 29, 2009
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for adjusting performance of integrated circuits
- Patent number 7,573,317
- Issue date Aug 11, 2009
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output device having parasitic transistor for increased current drive
- Patent number 7,511,533
- Issue date Mar 31, 2009
- Altera Corporation
- Hugh Sungki O
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Approach to reduce parasitic capacitance from dummy fill
- Patent number 7,470,630
- Issue date Dec 30, 2008
- Altera Corporation
- Shuxian Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for multi-gate silicon-on-insulator transistors
- Patent number 7,415,690
- Issue date Aug 19, 2008
- Altera Corporation
- Minchang Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast trigger ESD device for protection of integrated circuits
- Patent number 7,408,754
- Issue date Aug 5, 2008
- Altera Corporation
- Hugh Sung-Ki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus with varying gate oxide thickness
- Patent number 7,361,961
- Issue date Apr 22, 2008
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 7,348,827
- Issue date Mar 25, 2008
- Altera Corporation
- Irfan Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compact SCR device and method for integrated circuits
- Patent number 7,342,282
- Issue date Mar 11, 2008
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD device with low trigger voltage and low leakage
- Patent number 7,333,312
- Issue date Feb 19, 2008
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Effective I/O ESD protection device for high performance circuits
- Patent number 7,326,998
- Issue date Feb 5, 2008
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for multi-gate silicon-on-insulator transistors
- Patent number 7,307,445
- Issue date Dec 11, 2007
- Altera Corporation
- Minchang Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bipolar transistors with low base resistance for CMOS integrated ci...
- Patent number 7,285,454
- Issue date Oct 23, 2007
- Altera Corporation
- Minchang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage clamp circuit with reduced I/O capacitance
- Patent number 7,279,952
- Issue date Oct 9, 2007
- Altera Corporation
- Hugh Sungki O
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Local control of electrical and mechanical properties of copper int...
- Patent number 7,235,884
- Issue date Jun 26, 2007
- Altera Corporation
- Peter John McElheny
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for optimizing programmable logic device performance by red...
- Patent number 7,210,115
- Issue date Apr 24, 2007
- Altera Corporation
- Irfan Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stable programming circuitry for programmable integrated circuits
- Patent number 7,170,810
- Issue date Jan 30, 2007
- Altera Corporation
- Hugh Sungki O
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically-programmable transistor antifuses
- Patent number 7,157,782
- Issue date Jan 2, 2007
- Altera Corporation
- Chih-Ching Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for adjusting performance of integrated circuits
- Patent number 7,129,745
- Issue date Oct 31, 2006
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for multi-gate silicon-on-insulator transistors
- Patent number 7,112,997
- Issue date Sep 26, 2006
- Altera Corporation
- Minchang Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits with reduced standby power consumption
- Patent number 7,109,748
- Issue date Sep 19, 2006
- Altera Corporation
- Yow-Juang W Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for monitoring parasitic inductance
- Patent number 7,067,842
- Issue date Jun 27, 2006
- Altera Corporation
- Jayakannan Jayapalan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Apparatus and Methods for Adjusting Performance of Integrated Circuits
- Publication number 20090289696
- Publication date Nov 26, 2009
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Methods for Adjusting Performance of Programmable Log...
- Publication number 20080164936
- Publication date Jul 10, 2008
- Altera Corporation
- Irfan Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR MULTI-GATE SILICON-ON-INSULATOR TRANSISTORS
- Publication number 20080061821
- Publication date Mar 13, 2008
- Altera Corporation
- Minchang Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE OF INTEGRATED CIRCUITS
- Publication number 20070069764
- Publication date Mar 29, 2007
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESD device with low trigger voltage and low leakage
- Publication number 20070002507
- Publication date Jan 4, 2007
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS FOR MULTI-GATE SILICON-ON-INSULATOR TRANSISTORS
- Publication number 20060279333
- Publication date Dec 14, 2006
- Altera Corporation
- Minchang Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus with varying gate oxide thickness
- Publication number 20060237784
- Publication date Oct 26, 2006
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact SCR device and method for integrated circuits
- Publication number 20060054974
- Publication date Mar 16, 2006
- Altera Corporation
- Hugh Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and methods for adjusting performance of integrated circuits
- Publication number 20050280437
- Publication date Dec 22, 2005
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for adjusting performance of programmable log...
- Publication number 20050258862
- Publication date Nov 24, 2005
- Irfan Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Polysilicon gate doping level variation for reduced leakage current
- Publication number 20050003601
- Publication date Jan 6, 2005
- Peter McElheny
- H01 - BASIC ELECTRIC ELEMENTS

Yow Juang W. Liu

Person

Patents Grantslast 30 patents

Integrated circuits with nonvolatile memory elements

Memory element circuitry with stressed transistors

Apparatus and methods for adjusting performance of integrated circuits

Integrated circuits with nonvolatile memory elements

Apparatus and methods for electrostatic discharge circuitry with sn...

Method and device for electrostatic discharge protection

Electrically-programmable transistor antifuses

Method and device for electrostatic discharge protection

ESD protection structure

Apparatus and methods for adjusting performance of integrated circuits

Output device having parasitic transistor for increased current drive

Approach to reduce parasitic capacitance from dummy fill

Apparatus and methods for multi-gate silicon-on-insulator transistors

Fast trigger ESD device for protection of integrated circuits

Method and apparatus with varying gate oxide thickness

Apparatus and methods for adjusting performance of programmable log...

Compact SCR device and method for integrated circuits

ESD device with low trigger voltage and low leakage

Effective I/O ESD protection device for high performance circuits

Apparatus and methods for multi-gate silicon-on-insulator transistors

Bipolar transistors with low base resistance for CMOS integrated ci...

Voltage clamp circuit with reduced I/O capacitance

Local control of electrical and mechanical properties of copper int...

Methods for optimizing programmable logic device performance by red...

Stable programming circuitry for programmable integrated circuits

Electrically-programmable transistor antifuses

Apparatus and methods for adjusting performance of integrated circuits

Apparatus and methods for multi-gate silicon-on-insulator transistors

Integrated circuits with reduced standby power consumption

Method and apparatus for monitoring parasitic inductance

Patents Applicationslast 30 patents

Apparatus and Methods for Adjusting Performance of Integrated Circuits

Apparatus and Methods for Adjusting Performance of Programmable Log...

APPARATUS AND METHODS FOR MULTI-GATE SILICON-ON-INSULATOR TRANSISTORS

APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE OF INTEGRATED CIRCUITS

ESD device with low trigger voltage and low leakage

APPARATUS AND METHODS FOR MULTI-GATE SILICON-ON-INSULATOR TRANSISTORS

Method and apparatus with varying gate oxide thickness

Compact SCR device and method for integrated circuits

Apparatus and methods for adjusting performance of integrated circuits

Apparatus and methods for adjusting performance of programmable log...

Polysilicon gate doping level variation for reduced leakage current