Yung-Chin HOU

Person

Taipei City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits and manufacturing methods thereof
- Patent number 12,094,880
- Issue date Sep 17, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ali Keshavarzi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with thicker metal lines on lower metallization...
- Patent number 12,008,302
- Issue date Jun 11, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuang-Hung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor layout with different row heights
- Patent number 11,682,665
- Issue date Jun 20, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hui-Zhong Zhuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with thicker metal lines on lower metallization...
- Patent number 11,593,546
- Issue date Feb 28, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuang-Hung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits and manufacturing methods thereof
- Patent number 11,581,314
- Issue date Feb 14, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ali Keshavarzi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with thicker metal lines on lower metallization...
- Patent number 11,113,443
- Issue date Sep 7, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuang-Hung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Key structure convertible between digital and analog switch modes a...
- Patent number 11,017,966
- Issue date May 25, 2021
- Acer Incorporated
- Hung-Chi Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Machine-learning design enablement platform
- Patent number 11,017,149
- Issue date May 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Key structure convertible between digital and analog switch modes a...
- Patent number 10,714,281
- Issue date Jul 14, 2020
- Acer Incorporated
- Hung-Chi Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Machine-learning design enablement platform
- Patent number 10,678,973
- Issue date Jun 9, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits and manufacturing methods thereof
- Patent number 10,535,655
- Issue date Jan 14, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ali Keshavarzi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of component partitions on system on chip and device thereof
- Patent number 9,811,627
- Issue date Nov 7, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits and manufacturing methods thereof
- Patent number 9,312,260
- Issue date Apr 12, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ali Keshavarzi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of generating RC technology file
- Patent number 8,671,382
- Issue date Mar 11, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design in optical shrink technology node
- Patent number 8,671,367
- Issue date Mar 11, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Hsing Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design using DFM-enhanced architecture
- Patent number 8,631,366
- Issue date Jan 14, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Integrated circuit layouts with power rails under bottom metal layer
- Patent number 8,507,957
- Issue date Aug 13, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for non-shrinkable IP integration
- Patent number 8,504,965
- Issue date Aug 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Yi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having flexible layout architecture/boundaries
- Patent number 8,504,972
- Issue date Aug 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout and process of forming contact plugs
- Patent number 8,431,985
- Issue date Apr 30, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of generating RC technology file
- Patent number 8,418,112
- Issue date Apr 9, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on chip development with reconfigurable multi-project wafer...
- Patent number 8,261,219
- Issue date Sep 4, 2012
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kun-Lung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for cell boundary isolation in double patterning design
- Patent number 8,255,837
- Issue date Aug 28, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Lee-Chung Lu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Contact implement structure for high density design
- Patent number 8,217,469
- Issue date Jul 10, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Table-based DFM for accurate post-layout analysis
- Patent number 8,201,111
- Issue date Jun 12, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Table-based DFM for accurate post-layout analysis
- Patent number 8,001,494
- Issue date Aug 16, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and system of mixing poly pitch cell design under default...
- Patent number 7,932,566
- Issue date Apr 26, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gating in integrated circuits for leakage reduction
- Patent number 7,913,141
- Issue date Mar 22, 2011
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Lee-Chung Yu
- G01 - MEASURING TESTING
Information Patent Grant
Layout architecture for improving circuit performance
- Patent number 7,821,039
- Issue date Oct 26, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Li-Chun Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell without OD space effect in Y-direction
- Patent number 7,808,051
- Issue date Oct 5, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
POWER RAIL ARRANGEMENTS IN INTEGRATED CIRCUITS HAVING STACKED TRANS...
- Publication number 20240355707
- Publication date Oct 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin HOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
- Publication number 20240355821
- Publication date Oct 24, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- YUNG-CHIN HOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR CONTACTS AND METHODS OF FORMING THEREOF
- Publication number 20240304685
- Publication date Sep 12, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DISTRIBUTION STRUCTURE, MANUFACTURING METHOD, AND LAYOUT METHOD
- Publication number 20240303407
- Publication date Sep 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Cheng TZENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING
- Publication number 20240274585
- Publication date Aug 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin HOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20230275081
- Publication date Aug 31, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui-Zhong ZHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION...
- Publication number 20230205966
- Publication date Jun 29, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuang-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
- Publication number 20230197723
- Publication date Jun 22, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ali KESHAVARZI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS
- Publication number 20220384417
- Publication date Dec 1, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui-Zhong ZHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION...
- Publication number 20210390240
- Publication date Dec 16, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuang-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS
- Publication number 20200402968
- Publication date Dec 24, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui-Zhong ZHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Machine-Learning Design Enablement Platform
- Publication number 20200272777
- Publication date Aug 27, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
KEY STRUCTURE CONVERTIBLE BETWEEN DIGITAL AND ANALOG SWITCH MODES A...
- Publication number 20200273643
- Publication date Aug 27, 2020
- ACER INCORPORATED
- Hung-Chi Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
KEY STRUCTURE CONVERTIBLE BETWEEN DIGITAL AND ANALOG SWITCH MODES A...
- Publication number 20200185168
- Publication date Jun 11, 2020
- ACER INCORPORATED
- Hung-Chi Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
- Publication number 20200126986
- Publication date Apr 23, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ali KESHAVARZI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HOUSING STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20180356862
- Publication date Dec 13, 2018
- ACER INCORPORATED
- Chi-Hung Lai
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Application
MACHINE-LEARNING DESIGN ENABLEMENT PLATFORM
- Publication number 20180268096
- Publication date Sep 20, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF COMPONENT PARTITIONS ON SYSTEM ON CHIP AND DEVICE THEREOF
- Publication number 20170161420
- Publication date Jun 8, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yung-Chin HOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
- Publication number 20160372469
- Publication date Dec 22, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ali Keshavarzi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Generating RC Technology File
- Publication number 20130227514
- Publication date Aug 29, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Layouts with Power Rails under Bottom Metal Layer
- Publication number 20120280287
- Publication date Nov 8, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Generating RC Technology File
- Publication number 20120226479
- Publication date Sep 6, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Method for Non-Shrinkable IP Integration
- Publication number 20120084745
- Publication date Apr 5, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Yi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout and Process of Forming Contact Plugs
- Publication number 20120032268
- Publication date Feb 9, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
- Publication number 20110291200
- Publication date Dec 1, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ali KESHAVARZI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Table-Based DFM for Accurate Post-Layout Analysis
- Publication number 20110289466
- Publication date Nov 24, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin HOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOVEL CONTACT IMPLEMENT STRUCTURE FOR HIGH DENSITY DESIGN
- Publication number 20110140203
- Publication date Jun 16, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Design using DFM-Enhanced Architecture
- Publication number 20100281446
- Publication date Nov 4, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Standard Cells Having Flexible Layout Architecture/Boundaries
- Publication number 20100269081
- Publication date Oct 21, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for Cell Boundary Isolation in Double Patterning Design
- Publication number 20100196803
- Publication date Aug 5, 2010
- Lee-Chung Lu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Yung-Chin HOU

Person

Patents Grantslast 30 patents

Integrated circuits and manufacturing methods thereof

Integrated circuit with thicker metal lines on lower metallization...

Semiconductor layout with different row heights

Integrated circuit with thicker metal lines on lower metallization...

Integrated circuits and manufacturing methods thereof

Integrated circuit with thicker metal lines on lower metallization...

Key structure convertible between digital and analog switch modes a...

Machine-learning design enablement platform

Key structure convertible between digital and analog switch modes a...

Machine-learning design enablement platform

Integrated circuits and manufacturing methods thereof

Method of component partitions on system on chip and device thereof

Integrated circuits and manufacturing methods thereof

Method of generating RC technology file

Integrated circuit design in optical shrink technology node

Integrated circuit design using DFM-enhanced architecture

Integrated circuit layouts with power rails under bottom metal layer

Method for non-shrinkable IP integration

Standard cells having flexible layout architecture/boundaries

Layout and process of forming contact plugs

Method of generating RC technology file

System on chip development with reconfigurable multi-project wafer...

Methods for cell boundary isolation in double patterning design

Contact implement structure for high density design

Table-based DFM for accurate post-layout analysis

Table-based DFM for accurate post-layout analysis

Structure and system of mixing poly pitch cell design under default...

Power gating in integrated circuits for leakage reduction

Layout architecture for improving circuit performance

Standard cell without OD space effect in Y-direction

Patents Applicationslast 30 patents

POWER RAIL ARRANGEMENTS IN INTEGRATED CIRCUITS HAVING STACKED TRANS...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

TRANSISTOR CONTACTS AND METHODS OF FORMING THEREOF

POWER DISTRIBUTION STRUCTURE, MANUFACTURING METHOD, AND LAYOUT METHOD

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING

SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION...

INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF

METHOD OF SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS

INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION...

SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS

Machine-Learning Design Enablement Platform

KEY STRUCTURE CONVERTIBLE BETWEEN DIGITAL AND ANALOG SWITCH MODES A...

KEY STRUCTURE CONVERTIBLE BETWEEN DIGITAL AND ANALOG SWITCH MODES A...

INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF

HOUSING STRUCTURE AND MANUFACTURING METHOD THEREOF

MACHINE-LEARNING DESIGN ENABLEMENT PLATFORM

METHOD OF COMPONENT PARTITIONS ON SYSTEM ON CHIP AND DEVICE THEREOF

INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF

Method of Generating RC Technology File

Integrated Circuit Layouts with Power Rails under Bottom Metal Layer

Method of Generating RC Technology File

Design Method for Non-Shrinkable IP Integration

Layout and Process of Forming Contact Plugs

INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF

Table-Based DFM for Accurate Post-Layout Analysis

NOVEL CONTACT IMPLEMENT STRUCTURE FOR HIGH DENSITY DESIGN

Integrated Circuit Design using DFM-Enhanced Architecture

Standard Cells Having Flexible Layout Architecture/Boundaries

Methods for Cell Boundary Isolation in Double Patterning Design