Yutaka Nakamura

Person

Kyoto-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked, reconfigurable co-regulation of processing units for ultra...
- Patent number 11,687,148
- Issue date Jun 27, 2023
- International Business Machines Corporation
- Robert K. Montoye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cluster classification device, environment generation device, and e...
- Patent number 11,328,174
- Issue date May 10, 2022
- Daikin Industries, Ltd.
- Naoko Nakayama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing sequence for digital STDP synapse and LIF neuron-based neuro...
- Patent number 11,003,984
- Issue date May 11, 2021
- Samsung Electronics Co., Ltd.
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-stage gated-diode sense amplifier
- Patent number 10,930,325
- Issue date Feb 23, 2021
- International Business Machines Corporation
- Yutaka Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
LUT based synapse weight update scheme in STDP neuromorphic systems
- Patent number 10,891,543
- Issue date Jan 12, 2021
- Samsung Electronics Co., Ltd.
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digitial STDP synapse and LIF neuron-based neuromorphic system
- Patent number 10,762,419
- Issue date Sep 1, 2020
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sense amplifiers for wider I/O memory device
- Patent number 10,755,767
- Issue date Aug 25, 2020
- International Business Machines Corporation
- Yutaka Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
LUT based neuron membrane potential update scheme in STDP neuromorp...
- Patent number 10,748,058
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital STDP synapse and LIF neuron-based neuromorphic system
- Patent number 10,552,731
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual power rail cascode driver
- Patent number 10,360,958
- Issue date Jul 23, 2019
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Cascode complimentary dual level shifter
- Patent number 10,115,450
- Issue date Oct 30, 2018
- International Business Machines Corporation
- John K. DeBrosse
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Node isolation for protection from electrostatic discharge (ESD) da...
- Patent number 9,859,704
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Chen Guo
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Tie-off circuit with output node isolation for protection from elec...
- Patent number 9,601,921
- Issue date Mar 21, 2017
- International Business Machines Corporation
- Chen Guo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time division multiplexed limited switch dynamic logic
- Patent number 9,281,821
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time division multiplexed limited switch dynamic logic
- Patent number 9,276,580
- Issue date Mar 1, 2016
- International Business Machines Corporation
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time division multiplexed limited switch dynamic logic
- Patent number 9,030,234
- Issue date May 12, 2015
- International Business Machines Corporation
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time division multiplexed limited switch dynamic logic
- Patent number 9,030,235
- Issue date May 12, 2015
- International Business Machines Corporation
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Card device and socket
- Patent number 9,004,950
- Issue date Apr 14, 2015
- PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Yutaka Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed interface connector
- Patent number 8,708,749
- Issue date Apr 29, 2014
- Panasonic Corporation
- Hiroshi Suenaga
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,654,577
- Issue date Feb 18, 2014
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Time division multiplexed limited switch dynamic logic
- Patent number 8,604,832
- Issue date Dec 10, 2013
- International Business Machines Corporation
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,576,618
- Issue date Nov 5, 2013
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,570,793
- Issue date Oct 29, 2013
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,565,014
- Issue date Oct 22, 2013
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Time division multiplexed limited switch dynamic logic
- Patent number 8,493,093
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spin-torque transfer magneto-resistive memory architecture
- Patent number 8,456,899
- Issue date Jun 4, 2013
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Spin-torque transfer magneto-resistive memory architecture
- Patent number 8,456,901
- Issue date Jun 4, 2013
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Spin-torque transfer magneto-resistive memory architecture
- Patent number 8,446,757
- Issue date May 21, 2013
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between th...
- Patent number 8,437,181
- Issue date May 7, 2013
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory card
- Patent number 8,125,786
- Issue date Feb 28, 2012
- Panasonic Corporation
- Hidenobu Nishikawa
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
CLUSTER CLASSIFICATION DEVICE, ENVIRONMENT GENERATION DEVICE, AND E...
- Publication number 20210312226
- Publication date Oct 7, 2021
- DAIKIN INDUSTRIES, LTD.
- Naoko NAKAYAMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-STAGE GATED-DIODE SENSE AMPLIFIER
- Publication number 20200243120
- Publication date Jul 30, 2020
- International Business Machines Corporation
- Yutaka Nakamura
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIERS FOR WIDER I/O MEMORY DEVICES
- Publication number 20200227110
- Publication date Jul 16, 2020
- International Business Machines Corporation
- Yutaka Nakamura
- G11 - INFORMATION STORAGE
Information Patent Application
DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM
- Publication number 20190354845
- Publication date Nov 21, 2019
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL POWER RAIL CASCODE DRIVER
- Publication number 20180358062
- Publication date Dec 13, 2018
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
Timing Sequence for Digital STDP Synapse and LIF Neuron-based Neuro...
- Publication number 20170344885
- Publication date Nov 30, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM
- Publication number 20170185890
- Publication date Jun 29, 2017
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LUT BASED SYNAPSE WEIGHT UPDATE SCHEME IN STDP NEUROMORPHIC SYSTEMS
- Publication number 20170185889
- Publication date Jun 29, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LUT BASED NEURON MEMBRANE POTENTIAL UPDATE SCHEME IN STDP NEUROMORP...
- Publication number 20170185891
- Publication date Jun 29, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NODE ISOLATION FOR PROTECTION FROM ELECTROSTATIC DISCHARGE (ESD) DA...
- Publication number 20170141568
- Publication date May 18, 2017
- International Business Machines Corporation
- Chen Guo
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC
- Publication number 20150222267
- Publication date Aug 6, 2015
- International Business Machines Corporation
- LELAND CHANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC
- Publication number 20150194962
- Publication date Jul 9, 2015
- International Business Machines Corporation
- LELAND CHANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIE-OFF CIRCUIT WITH OUTPUT NODE ISOLATION FOR PROTECTION FROM ELEC...
- Publication number 20150188313
- Publication date Jul 2, 2015
- International Business Machines Corporation
- Chen Guo
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC
- Publication number 20140049289
- Publication date Feb 20, 2014
- International Business Machines Corporation
- LELAND CHANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CARD COMMUNICATION DEVICE
- Publication number 20140051353
- Publication date Feb 20, 2014
- PANASONIC CORPORATION
- Yutaka NAKAMURA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INPUT PROTECTION CIRCUIT
- Publication number 20130342943
- Publication date Dec 26, 2013
- PANASONIC CORPORATION
- Hisanori YUUKI
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC
- Publication number 20130328592
- Publication date Dec 12, 2013
- International Business Machines Corporation
- LELAND CHANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC
- Publication number 20130328593
- Publication date Dec 12, 2013
- Leland Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...
- Publication number 20130301347
- Publication date Nov 14, 2013
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...
- Publication number 20130265821
- Publication date Oct 10, 2013
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...
- Publication number 20130250672
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...
- Publication number 20130250673
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE, HOST DEVICE, AND STORAGE SYSTEM
- Publication number 20130238566
- Publication date Sep 12, 2013
- PANASONIC CORPORATION
- Yutaka NAKAMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-SPEED INTERFACE CONNECTOR
- Publication number 20130045635
- Publication date Feb 21, 2013
- Hiroshi Suenaga
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Spin-Torque Transfer Magneto-Resistive Memory Architecture
- Publication number 20120294071
- Publication date Nov 22, 2012
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
Spin-Torque Transfer Magneto-Resistive Memory Architecture
- Publication number 20120287705
- Publication date Nov 15, 2012
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
Spin-Torque Transfer Magneto-Resistive Memory Architecture
- Publication number 20120044754
- Publication date Feb 23, 2012
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
Shared bit line SMT MRAM array with shunting transistors between th...
- Publication number 20110317479
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
ANTENNA BUILT-IN MODULE, CARD TYPE INFORMATION DEVICE, AND METHODS...
- Publication number 20100163630
- Publication date Jul 1, 2010
- Matsushita Electric Industrial Co., Ltd.
- Shozo Ochi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CARD
- Publication number 20090254704
- Publication date Oct 8, 2009
- PANASONIC CORPORATION
- Yutaka Nakamura
- G06 - COMPUTING CALCULATING COUNTING

Yutaka Nakamura

Person

Patents Grantslast 30 patents

Stacked, reconfigurable co-regulation of processing units for ultra...

Cluster classification device, environment generation device, and e...

Timing sequence for digital STDP synapse and LIF neuron-based neuro...

Two-stage gated-diode sense amplifier

LUT based synapse weight update scheme in STDP neuromorphic systems

Digitial STDP synapse and LIF neuron-based neuromorphic system

Sense amplifiers for wider I/O memory device

LUT based neuron membrane potential update scheme in STDP neuromorp...

Digital STDP synapse and LIF neuron-based neuromorphic system

Dual power rail cascode driver

Cascode complimentary dual level shifter

Node isolation for protection from electrostatic discharge (ESD) da...

Tie-off circuit with output node isolation for protection from elec...

Time division multiplexed limited switch dynamic logic

Time division multiplexed limited switch dynamic logic

Time division multiplexed limited switch dynamic logic

Time division multiplexed limited switch dynamic logic

Card device and socket

High-speed interface connector

Shared bit line SMT MRAM array with shunting transistors between bi...

Time division multiplexed limited switch dynamic logic

Shared bit line SMT MRAM array with shunting transistors between bi...

Shared bit line SMT MRAM array with shunting transistors between bi...

Shared bit line SMT MRAM array with shunting transistors between bi...

Time division multiplexed limited switch dynamic logic

Spin-torque transfer magneto-resistive memory architecture

Spin-torque transfer magneto-resistive memory architecture

Spin-torque transfer magneto-resistive memory architecture

Shared bit line SMT MRAM array with shunting transistors between th...

Memory card

Patents Applicationslast 30 patents

CLUSTER CLASSIFICATION DEVICE, ENVIRONMENT GENERATION DEVICE, AND E...

TWO-STAGE GATED-DIODE SENSE AMPLIFIER

SENSE AMPLIFIERS FOR WIDER I/O MEMORY DEVICES

DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM

DUAL POWER RAIL CASCODE DRIVER

Timing Sequence for Digital STDP Synapse and LIF Neuron-based Neuro...

DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM

LUT BASED SYNAPSE WEIGHT UPDATE SCHEME IN STDP NEUROMORPHIC SYSTEMS

LUT BASED NEURON MEMBRANE POTENTIAL UPDATE SCHEME IN STDP NEUROMORP...

NODE ISOLATION FOR PROTECTION FROM ELECTROSTATIC DISCHARGE (ESD) DA...

TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC

TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC

TIE-OFF CIRCUIT WITH OUTPUT NODE ISOLATION FOR PROTECTION FROM ELEC...

TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC

CARD COMMUNICATION DEVICE

INPUT PROTECTION CIRCUIT

TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC

TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC

Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...

SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...

SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...

Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...

STORAGE DEVICE, HOST DEVICE, AND STORAGE SYSTEM

HIGH-SPEED INTERFACE CONNECTOR

Spin-Torque Transfer Magneto-Resistive Memory Architecture

Spin-Torque Transfer Magneto-Resistive Memory Architecture

Spin-Torque Transfer Magneto-Resistive Memory Architecture

Shared bit line SMT MRAM array with shunting transistors between th...

ANTENNA BUILT-IN MODULE, CARD TYPE INFORMATION DEVICE, AND METHODS...

MEMORY CARD