Zafer S. Kutlu

Person

Menlo Park, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Regulator circuit package techniques
- Patent number 11,955,437
- Issue date Apr 9, 2024
- Analog Devices International Unlimited Company
- Leonard Shtargot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional packaging techniques for power FET density improv...
- Patent number 11,476,232
- Issue date Oct 18, 2022
- Analog Devices International Unlimited Company
- Albert M. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic module for high power applications
- Patent number 11,410,977
- Issue date Aug 9, 2022
- Analog Devices International Unlimited Company
- John D. Brazzle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with overhang inductor
- Patent number 11,270,986
- Issue date Mar 8, 2022
- Analog Devices, Inc.
- Ahmadreza Odabaee
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Regulator circuit package techniques
- Patent number 11,037,883
- Issue date Jun 15, 2021
- Analog Devices International Unlimited Company
- Leonard Shtargot
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Process of grounding heat spreader/stiffener to a flip chip package...
- Patent number 7,968,999
- Issue date Jun 28, 2011
- LSI Corporation
- Zeki Z. Celik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with sputtered heat sink for improved th...
- Patent number 7,479,703
- Issue date Jan 20, 2009
- LSI Logic Corporation
- Zafer Kutlu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for avoiding dicing chip-outs in integrated ci...
- Patent number 7,354,790
- Issue date Apr 8, 2008
- LSI Logic Corporation
- Parthasarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Robust high density substrate design for thermal cycling reliability
- Patent number 7,345,245
- Issue date Mar 18, 2008
- LSI Logic Corporation
- Anand Govind
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low stress flip-chip package for low-K silicon technology
- Patent number 7,190,082
- Issue date Mar 13, 2007
- LSI Logic Corporation
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded strain gauge in printed circuit boards
- Patent number 7,096,748
- Issue date Aug 29, 2006
- LSI Logic Corporation
- Zafer S. Kutlu
- G01 - MEASURING TESTING
Information Patent Grant
Method of balanced coefficient of thermal expansion for flip chip b...
- Patent number 6,806,119
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal and mechanical attachment of a heatspreader to a flip-chip...
- Patent number 6,673,708
- Issue date Jan 6, 2004
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Balanced coefficient of thermal expansion for flip chip ball grid a...
- Patent number 6,639,321
- Issue date Oct 28, 2003
- LSI Logic Corporation
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal and mechanical attachment of a heatspreader to a flip-chip...
- Patent number 6,590,292
- Issue date Jul 8, 2003
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit test vehicle
- Patent number 6,534,968
- Issue date Mar 18, 2003
- LSI Logic Corporation
- Leah M. Miller
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced laminate flipchip package using a high CTE heatspreader
- Patent number 6,472,762
- Issue date Oct 29, 2002
- LSI Logic Corporation
- Zafer S. Kutlu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of planarizing die solder balls by employing a die's...
- Patent number 6,465,338
- Issue date Oct 15, 2002
- LSI Logic Corporation
- Sarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally-enhanced flip chip IC package with extruded heatspreader
- Patent number 6,114,761
- Issue date Sep 5, 2000
- LSI Logic Corporation
- Atila Mertol
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package having a stiffener dimensioned to receiv...
- Patent number 6,111,313
- Issue date Aug 29, 2000
- LSI Logic Corporation
- Zafer S. Kutlu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
REGULATOR CIRCUIT PACKAGE TECHNIQUES
- Publication number 20240282714
- Publication date Aug 22, 2024
- Analog Devices International Unlimited Company
- Leonard Shtargot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH OVERHANG INDUCTOR
- Publication number 20210358895
- Publication date Nov 18, 2021
- Analog Devices, Inc.
- Ahmadreza Odabaee
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
REGULATOR CIRCUIT PACKAGE TECHNIQUES
- Publication number 20210257313
- Publication date Aug 19, 2021
- Analog Devices International Unlimited Company
- Leonard Shtargot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL PACKAGING TECHNIQUES FOR POWER FET DENSITY IMPROV...
- Publication number 20200312814
- Publication date Oct 1, 2020
- Analog Devices International Unlimited Company
- Albert M. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REGULATOR CIRCUIT PACKAGE TECHNIQUES
- Publication number 20200161253
- Publication date May 21, 2020
- Analog Devices International Unlimited Company
- Leonard Shtargot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC MODULE FOR HIGH POWER APPLICATIONS
- Publication number 20200152614
- Publication date May 14, 2020
- Analog Devices International Unlimited Company
- John D. Brazzle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION
- Publication number 20120018901
- Publication date Jan 26, 2012
- LSI Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE...
- Publication number 20090218680
- Publication date Sep 3, 2009
- Zeki Z. Celik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED TH...
- Publication number 20090008767
- Publication date Jan 8, 2009
- Zafer Kutlu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH SOLDERED LID FOR IMPROVED THERMAL P...
- Publication number 20080290502
- Publication date Nov 27, 2008
- Zafer Kutlu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for avoiding dicing chip-outs in integrated ci...
- Publication number 20060160269
- Publication date Jul 20, 2006
- LSI Logic Corporation
- Parthasarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded strain gauge in printed circuit boards
- Publication number 20060021453
- Publication date Feb 2, 2006
- Zafer S. Kutlu
- G01 - MEASURING TESTING
Information Patent Application
Robust high density substrate design for thermal cycling reliability
- Publication number 20050077081
- Publication date Apr 14, 2005
- Anand Govind
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low stress flip-chip package for low-K silicon technology
- Publication number 20040188862
- Publication date Sep 30, 2004
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of balanced coefficient of thermal expansion for flip chip b...
- Publication number 20040121519
- Publication date Jun 24, 2004
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Underfill gap enhancement
- Publication number 20040070073
- Publication date Apr 15, 2004
- Shirish Shah
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Zafer S. Kutlu

Person

Patents Grantslast 30 patents

Regulator circuit package techniques

Three-dimensional packaging techniques for power FET density improv...

Electronic module for high power applications

Package with overhang inductor

Regulator circuit package techniques

Process of grounding heat spreader/stiffener to a flip chip package...

Integrated circuit package with sputtered heat sink for improved th...

Method and apparatus for avoiding dicing chip-outs in integrated ci...

Robust high density substrate design for thermal cycling reliability

Low stress flip-chip package for low-K silicon technology

Embedded strain gauge in printed circuit boards

Method of balanced coefficient of thermal expansion for flip chip b...

Thermal and mechanical attachment of a heatspreader to a flip-chip...

Balanced coefficient of thermal expansion for flip chip ball grid a...

Thermal and mechanical attachment of a heatspreader to a flip-chip...

Integrated circuit test vehicle

Enhanced laminate flipchip package using a high CTE heatspreader

Method of planarizing die solder balls by employing a die&#x00027;s...

Thermally-enhanced flip chip IC package with extruded heatspreader

Integrated circuit package having a stiffener dimensioned to receiv...

Patents Applicationslast 30 patents

REGULATOR CIRCUIT PACKAGE TECHNIQUES

PACKAGE WITH OVERHANG INDUCTOR

REGULATOR CIRCUIT PACKAGE TECHNIQUES

THREE-DIMENSIONAL PACKAGING TECHNIQUES FOR POWER FET DENSITY IMPROV...

REGULATOR CIRCUIT PACKAGE TECHNIQUES

ELECTRONIC MODULE FOR HIGH POWER APPLICATIONS

FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION

PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE...

INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED TH...

INTEGRATED CIRCUIT PACKAGE WITH SOLDERED LID FOR IMPROVED THERMAL P...

Method and apparatus for avoiding dicing chip-outs in integrated ci...

Embedded strain gauge in printed circuit boards

Robust high density substrate design for thermal cycling reliability

Low stress flip-chip package for low-K silicon technology

Method of balanced coefficient of thermal expansion for flip chip b...

Underfill gap enhancement

Method of planarizing die solder balls by employing a die's...