Zheng Tao

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Contact isolation in semiconductor devices
- Patent number 11,862,452
- Issue date Jan 2, 2024
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for filling a space in a semiconductor
- Patent number 11,824,122
- Issue date Nov 21, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried power rail contact formation
- Patent number 11,776,841
- Issue date Oct 3, 2023
- Imec VZW
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a mask layer
- Patent number 11,430,697
- Issue date Aug 30, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating stacked semiconductor device
- Patent number 11,107,812
- Issue date Aug 31, 2021
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pillar-shaped semiconductor device and method for producing the same
- Patent number 10,825,822
- Issue date Nov 3, 2020
- Unisantis Electronics Singapore Pte. Ltd.
- Fujio Masuoka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a pillar structure in a semiconductor layer
- Patent number 10,825,682
- Issue date Nov 3, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for forming horizontal nanowires and devices manufactured th...
- Patent number 10,790,382
- Issue date Sep 29, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of forming micro-pipes on a substrate and a structure formed...
- Patent number 10,493,378
- Issue date Dec 3, 2019
- Imec VZW
- Zheng Tao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming internal spacer for nanowires
- Patent number 10,153,341
- Issue date Dec 11, 2018
- Imec VZW
- Zheng Tao
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Self-aligned nanostructures for semiconductor devices
- Patent number 10,128,371
- Issue date Nov 13, 2018
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a field effect transistor device having an elect...
- Patent number 10,090,393
- Issue date Oct 2, 2018
- Imec VZW
- Steven Demuynck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning a substrate involving directed self-assembly
- Patent number 9,899,220
- Issue date Feb 20, 2018
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning an underlying layer
- Patent number 9,548,208
- Issue date Jan 17, 2017
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of providing an implanted region in a semiconductor structure
- Patent number 9,520,291
- Issue date Dec 13, 2016
- Imec VZW
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR DEVICE
- Publication number 20240154006
- Publication date May 9, 2024
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming an Interconnect Structure
- Publication number 20240036470
- Publication date Feb 1, 2024
- IMEC vzw
- Waikin Li
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20240006228
- Publication date Jan 4, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Structure for Determining an Overlay Error
- Publication number 20230207482
- Publication date Jun 29, 2023
- IMEC vzw
- Waikin Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnection Structure for a Semiconductor Device
- Publication number 20230170300
- Publication date Jun 1, 2023
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnection Structure for a Semiconductor Device
- Publication number 20230170255
- Publication date Jun 1, 2023
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Producing a Buried Interconnect Rail of an Integrated Ci...
- Publication number 20230046117
- Publication date Feb 16, 2023
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED POWER RAIL CONTACT FORMATION
- Publication number 20220181197
- Publication date Jun 9, 2022
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FILLING A SPACE IN A SEMICONDUCTOR
- Publication number 20210296500
- Publication date Sep 23, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contact Isolation in Semiconductor Devices
- Publication number 20210066116
- Publication date Mar 4, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20210028059
- Publication date Jan 28, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A MASK LAYER
- Publication number 20200328122
- Publication date Oct 15, 2020
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
- Publication number 20200168606
- Publication date May 28, 2020
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOPORE FORMED THROUGH FIN BY SELF-ALIGNMENT
- Publication number 20190271660
- Publication date Sep 5, 2019
- IMEC vzw
- Boon Teik Chan
- G01 - MEASURING TESTING
Information Patent Application
VERTICAL CHANNEL DEVICE AND METHOD OF FORMING SAME
- Publication number 20190198643
- Publication date Jun 27, 2019
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
- Publication number 20190148387
- Publication date May 16, 2019
- Unisantis Electronics Singapore PTE Ltd.
- Fujio MASUOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Horizontal Nanowires and Devices Manufactured Th...
- Publication number 20180182868
- Publication date Jun 28, 2018
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Internal Spacer for Nanowires
- Publication number 20180166534
- Publication date Jun 14, 2018
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Micro-pipes on a Substrate and a Structure Formed...
- Publication number 20180043283
- Publication date Feb 15, 2018
- IMEC vzw
- Zheng Tao
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Application
Self-Aligned Nanostructures for Semiconductor Devices
- Publication number 20170179281
- Publication date Jun 22, 2017
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Patterning a Substrate Involving Directed Self-Assembly
- Publication number 20170170017
- Publication date Jun 15, 2017
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Field Effect Transistor Device Having an Elect...
- Publication number 20170141199
- Publication date May 18, 2017
- IMEC vzw
- Steven Demuynck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Producing a Pillar Structure in a Semiconductor Layer
- Publication number 20170103889
- Publication date Apr 13, 2017
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Patterning an Underlying Layer
- Publication number 20160254161
- Publication date Sep 1, 2016
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Providing An Implanted Region In A Semiconductor Structure
- Publication number 20160196975
- Publication date Jul 7, 2016
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Contact isolation in semiconductor devices

Method for filling a space in a semiconductor

Buried power rail contact formation

Method of forming a mask layer

Method of fabricating stacked semiconductor device

Pillar-shaped semiconductor device and method for producing the same

Method for producing a pillar structure in a semiconductor layer

Method for forming horizontal nanowires and devices manufactured th...

Method of forming micro-pipes on a substrate and a structure formed...

Method of forming internal spacer for nanowires

Self-aligned nanostructures for semiconductor devices

Method for forming a field effect transistor device having an elect...

Method for patterning a substrate involving directed self-assembly

Method for patterning an underlying layer

Method of providing an implanted region in a semiconductor structure

Patents Applicationslast 30 patents

METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Method for Forming an Interconnect Structure

Method for Forming a Buried Metal Line in a Semiconductor Substrate

Method and Structure for Determining an Overlay Error

Interconnection Structure for a Semiconductor Device

Interconnection Structure for a Semiconductor Device

Method for Producing a Buried Interconnect Rail of an Integrated Ci...

BURIED POWER RAIL CONTACT FORMATION

METHOD FOR FILLING A SPACE IN A SEMICONDUCTOR

Contact Isolation in Semiconductor Devices

Method for Forming a Buried Metal Line in a Semiconductor Substrate

METHOD OF FORMING A MASK LAYER

STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

NANOPORE FORMED THROUGH FIN BY SELF-ALIGNMENT

VERTICAL CHANNEL DEVICE AND METHOD OF FORMING SAME

PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Method for Forming Horizontal Nanowires and Devices Manufactured Th...

Method of Forming Internal Spacer for Nanowires

Method of Forming Micro-pipes on a Substrate and a Structure Formed...

Self-Aligned Nanostructures for Semiconductor Devices

Method for Patterning a Substrate Involving Directed Self-Assembly

Method for Forming a Field Effect Transistor Device Having an Elect...

Method for Producing a Pillar Structure in a Semiconductor Layer

Method for Patterning an Underlying Layer

Method of Providing An Implanted Region In A Semiconductor Structure