Addressing or selecting of subparts of the device under test

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G01R31/318558

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318558Addressing or selecting of subparts of the device under test

Industries

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Patents Grantslast 30 patents

Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
System and method for access control of a plurality of instruments...
- Patent number 12,111,356
- Issue date Oct 8, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Vehicular drawing device
- Patent number 12,095,588
- Issue date Sep 17, 2024
- Denso Corporation
- Keiya Sakamoto
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Hybrid solver for integrated circuit diagnostics and testing
- Patent number 12,038,478
- Issue date Jul 16, 2024
- Xerox Corporation
- Aleksandar B. Feldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,025,649
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 11,782,092
- Issue date Oct 10, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D TAP and scan port architectures
- Patent number 11,762,014
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Controller for a memory component
- Patent number 11,755,350
- Issue date Sep 12, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,726,135
- Issue date Aug 15, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Transition fault testing of functionally asynchronous paths in an i...
- Patent number 11,709,203
- Issue date Jul 25, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Self-test circuit for an integrated circuit, and method for operati...
- Patent number 11,698,413
- Issue date Jul 11, 2023
- Infineon Technologies AG
- Juergen Alt
- G01 - MEASURING TESTING
Information Patent Grant
Direct scan access JTAG
- Patent number 11,693,055
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation circuitry in multi power domain s...
- Patent number 11,680,982
- Issue date Jun 20, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Falling clock edge JTAG bus routers
- Patent number 11,680,985
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 11,630,151
- Issue date Apr 18, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 11,549,983
- Issue date Jan 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface circuit
- Patent number 11,519,959
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,391,769
- Issue date Jul 19, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Controller for a memory component
- Patent number 11,334,377
- Issue date May 17, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistion fault testing of funtionally asynchronous paths in an i...
- Patent number 11,300,615
- Issue date Apr 12, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Direct scan access JTAG
- Patent number 11,255,908
- Issue date Feb 22, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,243,253
- Issue date Feb 8, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 11,231,461
- Issue date Jan 25, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS...
- Publication number 20240061041
- Publication date Feb 22, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION THROUGH PIN DATA ENCODING
- Publication number 20230375617
- Publication date Nov 23, 2023
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20230251309
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
ERROR DIAGNOSIS CIRCUIT AND METHOD FOR OPERATING A DEVICE
- Publication number 20230116822
- Publication date Apr 13, 2023
- INFINEON TECHNOLOGIES AG
- Veit KLEEBERGER
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20230058458
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20220341985
- Publication date Oct 27, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER FOR A MEMORY COMPONENT
- Publication number 20220276885
- Publication date Sep 1, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTION FAULT TESTING OF FUNTIONALLY ASYNCHRONOUS PATHS IN AN I...
- Publication number 20220196738
- Publication date Jun 23, 2022
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
DIRECT SCAN ACCESS JTAG
- Publication number 20220137134
- Publication date May 5, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20220107362
- Publication date Apr 7, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER FOR A MEMORY COMPONENT
- Publication number 20210333327
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20210333325
- Publication date Oct 28, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Withou...
- Publication number 20210333326
- Publication date Oct 28, 2021
- Peter Shun Shen Wang
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210325456
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VEHICULAR DRAWING DEVICE
- Publication number 20210226813
- Publication date Jul 22, 2021
- DENSO CORPORATION
- Keiya SAKAMOTO
- B60 - VEHICLES IN GENERAL
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20210148979
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DIE STACK TEST ARCHITECTURE AND METHOD
- Publication number 20210148963
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20210088584
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20210088587
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210072310
- Publication date Mar 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERVER SWITCH SYSTEM INCLUDING FIELD-PROGRAMMABLE GATE ARRAY UNIT F...
- Publication number 20200386812
- Publication date Dec 10, 2020
- Inventec (Pudong) Technology Corp.
- Chih-Jen Chin
- G01 - MEASURING TESTING
Information Patent Application
CIRCUITRY DESIGN METHOD AND STORAGE MEDIUM
- Publication number 20200300914
- Publication date Sep 24, 2020
- Kabushiki Kaisha Toshiba
- Yuki Watanabe
- G01 - MEASURING TESTING
Information Patent Application
DIRECT SCAN ACCESS JTAG
- Publication number 20200278394
- Publication date Sep 3, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Addressing or selecting of subparts of the device under test

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

3D tap and scan port architectures

Interface to full and reduced pin JTAG devices

System and method for access control of a plurality of instruments...

Scan compression through pin data encoding

Vehicular drawing device

Hybrid solver for integrated circuit diagnostics and testing

Integrated circuit die test architecture

Systems and methods for scan chain stitching

Reduced signaling interface method and apparatus

Scan compression through pin data encoding

Wafer scale testing using a 2 signal JTAG interface

Integrated circuit with reduced signaling interface

3D TAP and scan port architectures

Controller for a memory component

Integrated circuit die test architecture

Transition fault testing of functionally asynchronous paths in an i...

Self-test circuit for an integrated circuit, and method for operati...

Direct scan access JTAG

Automatic test pattern generation circuitry in multi power domain s...

Falling clock edge JTAG bus routers

Interface to full and reduced pin JTAG devices

Wafer scale testing using a 2 signal JTAG interface

3D tap and scan port architectures

Reduced signaling interface circuit

Integrated circuit die test architecture

Controller for a memory component

Transistion fault testing of funtionally asynchronous paths in an i...

Direct scan access JTAG

Wafer scale testing using a 2 signal JTAG interface

3D tap and scan port architectures

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS...

3D TAP & SCAN PORT ARCHITECTURES

SCAN COMPRESSION THROUGH PIN DATA ENCODING

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

FALLING CLOCK EDGE JTAG BUS ROUTERS

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

3D TAP & SCAN PORT ARCHITECTURES

ERROR DIAGNOSIS CIRCUIT AND METHOD FOR OPERATING A DEVICE

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

CONTROLLER FOR A MEMORY COMPONENT

TRANSISTION FAULT TESTING OF FUNTIONALLY ASYNCHRONOUS PATHS IN AN I...

DIRECT SCAN ACCESS JTAG

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

3D TAP & SCAN PORT ARCHITECTURES

CONTROLLER FOR A MEMORY COMPONENT

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Withou...

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

VEHICULAR DRAWING DEVICE

FALLING CLOCK EDGE JTAG BUS ROUTERS

DIE STACK TEST ARCHITECTURE AND METHOD

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

3D TAP & SCAN PORT ARCHITECTURES

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

SERVER SWITCH SYSTEM INCLUDING FIELD-PROGRAMMABLE GATE ARRAY UNIT F...

CIRCUITRY DESIGN METHOD AND STORAGE MEDIUM

DIRECT SCAN ACCESS JTAG