Addressing or selecting of test units

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CPC
G01R31/31722

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31722Addressing or selecting of test units

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random number generation testing systems and methods
- Patent number 12,135,352
- Issue date Nov 5, 2024
- Advantest Corporation
- Marilyn Kushnick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,092,687
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system, related integrated circuit, device and method
- Patent number 12,019,118
- Issue date Jun 25, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Roberto Colombo
- G01 - MEASURING TESTING
Information Patent Grant
Pattern generation system with pin function mapping
- Patent number 11,977,115
- Issue date May 7, 2024
- Yangtze Memory Technologies Co., Ltd.
- Feng Ru
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test chip test system
- Patent number 11,959,964
- Issue date Apr 16, 2024
- SEMITRONIX CORPORATION
- Jiabai Cheng
- G01 - MEASURING TESTING
Information Patent Grant
Benchmark circuit on a semiconductor wafer and method for operating...
- Patent number 11,927,628
- Issue date Mar 12, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chu-Feng Liao
- G01 - MEASURING TESTING
Information Patent Grant
System and method for distributed execution of a sequence processin...
- Patent number 11,907,755
- Issue date Feb 20, 2024
- Rohde & Schwarz GmbH & Co. KG
- Sebastian Roeglinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed control system, automatic analysis device, and automati...
- Patent number 11,863,374
- Issue date Jan 2, 2024
- HITACHI HIGH-TECH CORPORATION
- Takafumi Hasegawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 11,835,578
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for allocating addresses and corresponding units
- Patent number 11,835,577
- Issue date Dec 5, 2023
- Christoph Heldeis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interfaces for wireless debugging
- Patent number 11,709,202
- Issue date Jul 25, 2023
- Intel Corporation
- Sankaran M. Menon
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test chip
- Patent number 11,668,748
- Issue date Jun 6, 2023
- SEMITRONIX CORPORATION
- Fan Lan
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface circuit
- Patent number 11,519,959
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 11,262,402
- Issue date Mar 1, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Addressable test system with address register
- Patent number 11,243,251
- Issue date Feb 8, 2022
- SEMITRONIX CORPORATION
- Fan Lan
- G01 - MEASURING TESTING
Information Patent Grant
Entering home state after soft reset signal after address match
- Patent number 11,079,431
- Issue date Aug 3, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Testing fuse configurations in semiconductor devices
- Patent number 11,009,548
- Issue date May 18, 2021
- RAMBUS INC.
- Adrian E. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interfaces for wireless debugging
- Patent number 10,845,413
- Issue date Nov 24, 2020
- Intel IP Corporation
- Sankaran M. Menon
- G01 - MEASURING TESTING
Information Patent Grant
Single pin test interface for pin limited systems
- Patent number 10,816,597
- Issue date Oct 27, 2020
- Silicon Laboratories Inc.
- Huanhui Zhan
- G01 - MEASURING TESTING
Information Patent Grant
Functional, tap, trace circuitry with multiplexed tap, trace data o...
- Patent number 10,794,953
- Issue date Oct 6, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Addressable test chip with sensing circuit
- Patent number 10,725,102
- Issue date Jul 28, 2020
- SEMITRONIX CORPORATION
- Fan Lan
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test chip with multiple-stage transmission gates
- Patent number 10,725,101
- Issue date Jul 28, 2020
- SEMITRONIX CORPORATION
- Fan Lan
- G01 - MEASURING TESTING
Information Patent Grant
Memory circuit march testing
- Patent number 10,408,876
- Issue date Sep 10, 2019
- Oracle International Corporation
- Thomas Ziaja
- G01 - MEASURING TESTING
Information Patent Grant
Clock selection circuit and test clock generation circuit for LBIST...
- Patent number 10,393,804
- Issue date Aug 27, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Electronic system and signal switching circuit
- Patent number 10,340,896
- Issue date Jul 2, 2019
- Wiwynn Corporation
- Che-Wei Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Address/instruction registers, target domain interfaces, control in...
- Patent number 10,330,729
- Issue date Jun 25, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trace domain controller with test data I/O/control, internal contro...
- Patent number 10,317,461
- Issue date Jun 11, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATTERN GENERATION SYSTEM WITH PIN FUNCTION MAPPING
- Publication number 20240230756
- Publication date Jul 11, 2024
- Yangtze Memory Technologies Co., Ltd.
- Feng Ru
- G01 - MEASURING TESTING
Information Patent Application
BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...
- Publication number 20240175920
- Publication date May 30, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- CHU-FENG LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING TEST CIRCUITRY FOR MEMORY SUB-SYSTEMS
- Publication number 20240142520
- Publication date May 2, 2024
- NXP USA, Inc.
- Alexander Hoefler
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240019489
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CHECKING DFT CIRCUIT, TEST PLATFORM, STORAGE MEDIUM AND...
- Publication number 20230358805
- Publication date Nov 9, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Teng SHI
- G01 - MEASURING TESTING
Information Patent Application
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
- Publication number 20230349969
- Publication date Nov 2, 2023
- STMicroelectronics International N.V.
- Roberto Colombo
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST CHIP TEST SYSTEM
- Publication number 20230324458
- Publication date Oct 12, 2023
- Semitronix Corporation
- Jiabai CHENG
- G01 - MEASURING TESTING
Information Patent Application
CHIP TEST CIRCUIT AND CIRCUIT TEST METHOD
- Publication number 20230204660
- Publication date Jun 29, 2023
- Huawei Technologies Co., Ltd
- Changming CUI
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT IN CHIP AND CIRCUIT TEST METHOD
- Publication number 20230204661
- Publication date Jun 29, 2023
- Huawei Technologies Co., Ltd
- Yu HUANG
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20230058458
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...
- Publication number 20230014148
- Publication date Jan 19, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- CHU-FENG LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND DEVICES FOR INTELLIGENT INTEGRATED TESTING
- Publication number 20220390512
- Publication date Dec 8, 2022
- TestEye Technologies Inc.
- Edward Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL-EQUIVALENT-TIME FLASH ARRAY DIGITIZER OSCILLOSCOPE ARCHITECTURE
- Publication number 20220334180
- Publication date Oct 20, 2022
- Tektronix, Inc.
- John J. Pickerd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATTERN GENERATION SYSTEM WITH PIN FUNCTION MAPPING
- Publication number 20220317185
- Publication date Oct 6, 2022
- YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Feng Ru
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST CHIP
- Publication number 20220146573
- Publication date May 12, 2022
- Semitronix Corporation
- Fan LAN
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20220146574
- Publication date May 12, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR ALLOCATING ADDRESSES AND CORRESPONDING UNITS
- Publication number 20220065928
- Publication date Mar 3, 2022
- Christoph HELDEIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210325456
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Random Number Generation Testing Systems and Methods
- Publication number 20210302496
- Publication date Sep 30, 2021
- Advantest Corporation
- Marilyn Kushnick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR TEST AND MEASUREMENT INSTRUMENTATION DATA COLLECTION AND...
- Publication number 20210286004
- Publication date Sep 16, 2021
- Tektronix, Inc.
- Frederick B. Kuhlman
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR DISTRIBUTED EXECUTION OF A SEQUENCE PROCESSIN...
- Publication number 20210157637
- Publication date May 27, 2021
- ROHDE & SCHWARZ GMBH & CO. KG
- Sebastian ROEGLINGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210072310
- Publication date Mar 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACES FOR WIRELESS DEBUGGING
- Publication number 20210048476
- Publication date Feb 18, 2021
- Intel IP Corporation
- Sankaran M. Menon
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20200386810
- Publication date Dec 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESSABLE TEST SYSTEM WITH ADDRESS REGISTER
- Publication number 20200355742
- Publication date Nov 12, 2020
- Semitronix Corporation
- Fan LAN
- G01 - MEASURING TESTING
Information Patent Application
TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
- Publication number 20190353707
- Publication date Nov 21, 2019
- RAMBUS INC.
- Adrian E. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20190265295
- Publication date Aug 29, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20190250211
- Publication date Aug 15, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESSABLE TEST CHIP WITH MULTIPLE-STAGE TRANSMISSION GATES
- Publication number 20190235021
- Publication date Aug 1, 2019
- Semitronix Corporation
- Fan LAN
- G01 - MEASURING TESTING

Addressing or selecting of test units

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Selectable JTAG or trace access with data store and output

Random number generation testing systems and methods

Selectable JTAG or trace access with data store and output

Processing system, related integrated circuit, device and method

Pattern generation system with pin function mapping

Addressable test chip test system

Benchmark circuit on a semiconductor wafer and method for operating...

System and method for distributed execution of a sequence processin...

Reduced signaling interface method and apparatus

Distributed control system, automatic analysis device, and automati...

Selectable JTAG or trace access with data store and output

Method for allocating addresses and corresponding units

Integrated circuit with reduced signaling interface

Interfaces for wireless debugging

Addressable test chip

Reduced signaling interface circuit

Selectable JTAG or trace access with data store and output

Addressable test system with address register

Entering home state after soft reset signal after address match

Testing fuse configurations in semiconductor devices

Interfaces for wireless debugging

Single pin test interface for pin limited systems

Functional, tap, trace circuitry with multiplexed tap, trace data o...

Addressable test chip with sensing circuit

Addressable test chip with multiple-stage transmission gates

Memory circuit march testing

Clock selection circuit and test clock generation circuit for LBIST...

Electronic system and signal switching circuit

Address/instruction registers, target domain interfaces, control in...

Trace domain controller with test data I/O/control, internal contro...

Patents Applicationslast 30 patents

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

PATTERN GENERATION SYSTEM WITH PIN FUNCTION MAPPING

BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...

INTEGRATED CIRCUIT HAVING TEST CIRCUITRY FOR MEMORY SUB-SYSTEMS

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

METHOD FOR CHECKING DFT CIRCUIT, TEST PLATFORM, STORAGE MEDIUM AND...

PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

ADDRESSABLE TEST CHIP TEST SYSTEM

CHIP TEST CIRCUIT AND CIRCUIT TEST METHOD

TEST CIRCUIT IN CHIP AND CIRCUIT TEST METHOD

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...

SYSTEMS AND DEVICES FOR INTELLIGENT INTEGRATED TESTING

REAL-EQUIVALENT-TIME FLASH ARRAY DIGITIZER OSCILLOSCOPE ARCHITECTURE

PATTERN GENERATION SYSTEM WITH PIN FUNCTION MAPPING

ADDRESSABLE TEST CHIP

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

METHOD FOR ALLOCATING ADDRESSES AND CORRESPONDING UNITS

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

Random Number Generation Testing Systems and Methods

SYSTEM FOR TEST AND MEASUREMENT INSTRUMENTATION DATA COLLECTION AND...

SYSTEM AND METHOD FOR DISTRIBUTED EXECUTION OF A SEQUENCE PROCESSIN...

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

INTERFACES FOR WIRELESS DEBUGGING

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

ADDRESSABLE TEST SYSTEM WITH ADDRESS REGISTER

TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

ADDRESSABLE TEST CHIP WITH MULTIPLE-STAGE TRANSMISSION GATES