Aligning

Industry

CPC
H01L2224/8212

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/8212Aligning

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method for forming chip packages and a chip package having a chipse...
- Patent number 12,087,734
- Issue date Sep 10, 2024
- Yibu Semiconductor Co., Ltd.
- Weiping Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redistribution layer (RDL) layouts for integrated circuits
- Patent number 12,021,054
- Issue date Jun 25, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheng-Yuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redistribution layer (RDL) layouts for integrated circuits
- Patent number 11,791,299
- Issue date Oct 17, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheng-Yuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of adaptive patterning for panelize...
- Patent number 9,978,655
- Issue date May 22, 2018
- Deca Technologies Inc.
- Christopher M. Scanlan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive patterning for panelized packaging
- Patent number 9,520,331
- Issue date Dec 13, 2016
- Deca Technologies Inc.
- Christopher M. Scanlan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and method of adaptive patterning for panelize...
- Patent number 9,397,069
- Issue date Jul 19, 2016
- Deca Technologies Inc.
- Christopher M. Scanlan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Redistribution Layer (RDL) Layouts for Integrated Circuits
- Publication number 20230378116
- Publication date Nov 23, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
- Cheng-Yuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Chip Packages and a Chip Package
- Publication number 20220181295
- Publication date Jun 9, 2022
- Yibu Semiconductor Co., Ltd.
- Weiping LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDISTRIBUTION LAYER (RDL) LAYOUTS FOR INTEGRATED CIRCUITS
- Publication number 20190164924
- Publication date May 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cheng-Yuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE PATTERNING FOR PANELIZED PACKAGING
- Publication number 20130249088
- Publication date Sep 26, 2013
- DECA TECHNOLOGIES INC
- Christopher M. Scanlan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE PATTERNING FOR PANELIZED PACKAGING
- Publication number 20130241074
- Publication date Sep 19, 2013
- DECA TECHNOLOGIES INC
- Christopher M. Scanlan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE PATTERNING FOR PANELIZED PACKAGING
- Publication number 20130167102
- Publication date Jun 27, 2013
- DECA TECHNOLOGIES INC
- Timothy L. Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE PATTERNING FOR PANELIZED PACKAGING
- Publication number 20110202896
- Publication date Aug 18, 2011
- DECA TECHNOLOGIES INC.
- Christopher M. Scanlan
- G06 - COMPUTING CALCULATING COUNTING

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method for forming chip packages and a chip package having a chipse...

Redistribution layer (RDL) layouts for integrated circuits

Redistribution layer (RDL) layouts for integrated circuits

Semiconductor device and method of adaptive patterning for panelize...

Adaptive patterning for panelized packaging

Semiconductor device and method of adaptive patterning for panelize...

Patents Applicationslast 30 patents

Redistribution Layer (RDL) Layouts for Integrated Circuits

Method for Forming Chip Packages and a Chip Package

REDISTRIBUTION LAYER (RDL) LAYOUTS FOR INTEGRATED CIRCUITS

ADAPTIVE PATTERNING FOR PANELIZED PACKAGING

ADAPTIVE PATTERNING FOR PANELIZED PACKAGING

ADAPTIVE PATTERNING FOR PANELIZED PACKAGING

ADAPTIVE PATTERNING FOR PANELIZED PACKAGING