Aluminium arsenide [AlAs]

Industry

CPC
H01L2924/10322

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Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Current Industry

H01L2924/10322Aluminium arsenide [AlAs]

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method to minimize stress on stack via
- Patent number 12,080,600
- Issue date Sep 3, 2024
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of stacking semiconductor die for s...
- Patent number 11,881,476
- Issue date Jan 23, 2024
- Semtech Corporation
- Changjun Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of stacking semiconductor die for s...
- Patent number 11,373,990
- Issue date Jun 28, 2022
- Semtech Corporation
- Changjun Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming modular 3D semiconductor...
- Patent number 11,211,359
- Issue date Dec 28, 2021
- Semiconductor Components Industries, LLC
- Francis J. Carney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method to minimize stress on stack via
- Patent number 10,804,153
- Issue date Oct 13, 2020
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming 3D dual side die embedde...
- Patent number 10,510,703
- Issue date Dec 17, 2019
- STATS ChipPAC Pte. Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming small Z semiconductor pa...
- Patent number 9,899,285
- Issue date Feb 20, 2018
- Semtech Corporation
- Kok Khoon Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming conductive vias using ba...
- Patent number 9,865,524
- Issue date Jan 9, 2018
- STATS ChipPAC Pte. Ltd.
- Duk Ju Na
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming 3D dual side die embedde...
- Patent number 9,691,707
- Issue date Jun 27, 2017
- STATS ChipPAC Pte. Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming 3D dual side die embedde...
- Patent number 9,362,161
- Issue date Jun 7, 2016
- STATS ChipPAC, Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding method
- Patent number 8,641,859
- Issue date Feb 4, 2014
- Thin Materials AG
- Franz Richter
- B32 - LAYERED PRODUCTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method to Minimize Stress on Stack Via
- Publication number 20200402855
- Publication date Dec 24, 2020
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method to Minimize Stress on Stack Via
- Publication number 20160276237
- Publication date Sep 22, 2016
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Conductive Vias Using Ba...
- Publication number 20140300002
- Publication date Oct 9, 2014
- STATS ChipPAC, Ltd.
- Duk Ju Na
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDING METHOD
- Publication number 20110272092
- Publication date Nov 10, 2011
- THIN MATERIALS AG
- Franz Richter
- B32 - LAYERED PRODUCTS

Aluminium arsenide [AlAs]

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor device and method to minimize stress on stack via

Semiconductor device and method of stacking semiconductor die for s...

Semiconductor device and method of stacking semiconductor die for s...

Semiconductor device and method of forming modular 3D semiconductor...

Semiconductor device and method to minimize stress on stack via

Semiconductor device and method of forming 3D dual side die embedde...

Semiconductor device and method of forming small Z semiconductor pa...

Semiconductor device and method of forming conductive vias using ba...

Semiconductor device and method of forming 3D dual side die embedde...

Semiconductor device and method of forming 3D dual side die embedde...

Bonding method

Patents Applicationslast 30 patents

Semiconductor Device and Method to Minimize Stress on Stack Via

Semiconductor Device and Method to Minimize Stress on Stack Via

Semiconductor Device and Method of Forming Conductive Vias Using Ba...

BONDING METHOD