Applying a precursor material

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H01L2224/03829

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/03829Applying a precursor material

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Patents Grantslast 30 patents

Information Patent Grant
Wafer-level package including under bump metal layer
- Patent number 11,862,589
- Issue date Jan 2, 2024
- Samsung Electronics Co., Ltd.
- Hyung Sun Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level package including under bump metal layer
- Patent number 11,810,878
- Issue date Nov 7, 2023
- Samsung Electronics Co., Ltd.
- Hyung Sun Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level package including under bump metal layer
- Patent number 11,107,783
- Issue date Aug 31, 2021
- Samsung Electronics Co., Ltd.
- Hyung Sun Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip alignment utilizing superomniphobic surface treatment of silic...
- Patent number 10,396,050
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Eric J. Campbell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid low metal loading flux
- Patent number 9,950,393
- Issue date Apr 24, 2018
- Intel Corporation
- Rajen S. Sidhu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor packaging and manufacturing method thereof
- Patent number 9,935,044
- Issue date Apr 3, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsiu-Jen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip alignment utilizing superomniphobic surface treatment of silic...
- Patent number 9,859,244
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Eric J. Campbell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal to metal bonding for stacked (3D) integrated circuits
- Patent number 9,673,176
- Issue date Jun 6, 2017
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal to metal bonding for stacked (3D) integrated circuits
- Patent number 9,666,563
- Issue date May 30, 2017
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal to metal bonding for stacked (3D) integrated circuits
- Patent number 9,653,431
- Issue date May 16, 2017
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal to metal bonding for stacked (3D) integrated circuits
- Patent number 9,653,432
- Issue date May 16, 2017
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal to metal bonding for stacked (3D) integrated circuits
- Patent number 9,515,051
- Issue date Dec 6, 2016
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packaging and manufacturing method thereof
- Patent number 9,355,927
- Issue date May 31, 2016
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hsiu-Jen Lin
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER
- Publication number 20210358874
- Publication date Nov 18, 2021
- Samsung Electronics Co., Ltd.
- Hyung Sun JANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER
- Publication number 20210091026
- Publication date Mar 25, 2021
- Samsung Electronics Co., Ltd.
- Hyung Sun JANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER
- Publication number 20200161261
- Publication date May 21, 2020
- Samsung Electronics Co., Ltd.
- Hyung Sun JANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID LOW METAL LOADING FLUX
- Publication number 20180236609
- Publication date Aug 23, 2018
- Intel Corporation
- Rajen S. SIDHU
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILIC...
- Publication number 20170278817
- Publication date Sep 28, 2017
- International Business Machines Corporation
- Eric J. CAMPBELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS
- Publication number 20140374903
- Publication date Dec 25, 2014
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS
- Publication number 20140191418
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID LOW METAL LOADING FLUX
- Publication number 20130341379
- Publication date Dec 26, 2013
- Rajen S. Sidhu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
CONDUCTIVE BONDING MATERIAL, METHOD OF MANUFACTURING THE SAME, AND...
- Publication number 20130313309
- Publication date Nov 28, 2013
- Masayuki KITAJIMA
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR DEVICE INTERCONNECT
- Publication number 20130105993
- Publication date May 2, 2013
- GENERAL ELECTRIC COMPANY
- Raj BAHADUR
- H01 - BASIC ELECTRIC ELEMENTS

Applying a precursor material

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Wafer-level package including under bump metal layer

Wafer-level package including under bump metal layer

Wafer-level package including under bump metal layer

Chip alignment utilizing superomniphobic surface treatment of silic...

Hybrid low metal loading flux

Semiconductor packaging and manufacturing method thereof

Chip alignment utilizing superomniphobic surface treatment of silic...

Metal to metal bonding for stacked (3D) integrated circuits

Metal to metal bonding for stacked (3D) integrated circuits

Metal to metal bonding for stacked (3D) integrated circuits

Metal to metal bonding for stacked (3D) integrated circuits

Metal to metal bonding for stacked (3D) integrated circuits

Semiconductor packaging and manufacturing method thereof

Patents Applicationslast 30 patents

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

HYBRID LOW METAL LOADING FLUX

CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILIC...

METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS

METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS

HYBRID LOW METAL LOADING FLUX

CONDUCTIVE BONDING MATERIAL, METHOD OF MANUFACTURING THE SAME, AND...

SEMICONDUCTOR DEVICE INTERCONNECT