Arrangements for interconnecting storage elements electrically

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G11C5/06Arrangements for interconnecting storage elements electrically

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Patents Grantslast 30 patents

Information Patent Grant
Decoder architectures for three-dimensional memory devices
- Patent number 12,236,999
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip bump interface compatible with different orientations and type...
- Patent number 12,237,287
- Issue date Feb 25, 2025
- Xilinx, Inc.
- Ygal Arbel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device, memory device, and electronic device
- Patent number 12,230,314
- Issue date Feb 18, 2025
- Semiconductor Energy Laboratory Co., Ltd.
- Tatsuya Onuki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 12,230,359
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including a word line with portions with different si...
- Patent number 12,230,318
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 12,232,321
- Issue date Feb 18, 2025
- Kioxia Corporation
- Go Oike
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system
- Patent number 12,224,033
- Issue date Feb 11, 2025
- Kioxia Corporation
- Akira Katayama
- G11 - INFORMATION STORAGE
Information Patent Grant
Fabrication method of buried wordline structure
- Patent number 12,224,323
- Issue date Feb 11, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Yong Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 12,224,031
- Issue date Feb 11, 2025
- SK hynix Inc.
- Jung Dal Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for fabricating the same
- Patent number 12,223,989
- Issue date Feb 11, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Harry-Hak-Lay Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having word line structure
- Patent number 12,224,328
- Issue date Feb 11, 2025
- NANYA TECHNOLOGY CORPORATION
- Cheng-Yan Ji
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array connections
- Patent number 12,217,790
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chieh Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for depositing a molybdenum nitride film on a surface of a...
- Patent number 12,215,416
- Issue date Feb 4, 2025
- ASM IP Holding B.V.
- Eric Christopher Stevens
- G11 - INFORMATION STORAGE
Information Patent Grant
Component inter-digitated vias and leads
- Patent number 12,218,056
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Christopher Kinney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device and method of forming the same
- Patent number 12,217,817
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jung-Piao Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 12,219,767
- Issue date Feb 4, 2025
- Kioxia Corporation
- Tomoya Sanuki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated assemblies having transistor body regions coupled to car...
- Patent number 12,219,758
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Kamal M. Karda
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor wiring device and method
- Patent number 12,217,816
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Hidenori Yamaguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Control circuit on memory chip and dynamic random access memory
- Patent number 12,211,542
- Issue date Jan 28, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Jiarui Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to manufacture ferroelectric memory devices
- Patent number 12,211,538
- Issue date Jan 28, 2025
- Micron Technology, Inc.
- Giorgio Servalli
- G11 - INFORMATION STORAGE
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device having memory chip bonded to a CMOS chi...
- Patent number 12,211,544
- Issue date Jan 28, 2025
- Kioxia Corporation
- Hiroshi Maejima
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor storage device comprising a one-port SRAM cell formed...
- Patent number 12,213,298
- Issue date Jan 28, 2025
- SOCIONEXT INC.
- Masanobu Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor storage device
- Patent number 12,213,312
- Issue date Jan 28, 2025
- Kioxia Corporation
- Kaihei Kato
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-die package
- Patent number 12,205,667
- Issue date Jan 21, 2025
- Realtek Semiconductor Corp.
- Sheng-Feng Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,205,642
- Issue date Jan 21, 2025
- Kioxia Corporation
- Kunifumi Suzuki
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having physical unclonable function and memory system...
- Patent number 12,205,643
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Jooyong Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory array with dual-level peripheral circuits...
- Patent number 12,207,459
- Issue date Jan 21, 2025
- SanDisk Technologies LLC
- Yuki Mizutani
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 12,207,471
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Hae-min Lee
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICES WITH CONDUCTIVE SPACERS
- Publication number 20250063736
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sai-Hooi Yeong
- G11 - INFORMATION STORAGE
Information Patent Application
NAND String Utilizing Floating Body Memory Cell
- Publication number 20250063718
- Publication date Feb 20, 2025
- Zeno Semiconductor, Inc.
- Benjamin S. Louie
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20250061931
- Publication date Feb 20, 2025
- SK HYNIX INC.
- Take Kyun WOO
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS AND METHOD FOR MANUFACT...
- Publication number 20250054522
- Publication date Feb 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Li CHIANG
- G11 - INFORMATION STORAGE
Information Patent Application
TERNARY CONTENT-ADDRESSABLE MEMORY CELLS AND METHODS FOR FORMING TH...
- Publication number 20250054546
- Publication date Feb 13, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Gerben Doornbos
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURES OF SRAM CELL AND METHODS OF FABRICATING THE SAME
- Publication number 20250056785
- Publication date Feb 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kuan-Chung Chiu
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20250054521
- Publication date Feb 13, 2025
- KIOXIA Corporation
- Masato SUGITA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY OF INITIALIZATION AT MEMORY DIE
- Publication number 20250044965
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- James S. Rehmeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHODS REGARDI...
- Publication number 20250038045
- Publication date Jan 30, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for forming layout pattern of static random access memory
- Publication number 20250040228
- Publication date Jan 30, 2025
- UNITED MICROELECTRONICS CORP.
- Chun-Hsien Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20250037746
- Publication date Jan 30, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE
- Publication number 20250037743
- Publication date Jan 30, 2025
- SK HYNIX INC.
- Nam Jae LEE
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20250040140
- Publication date Jan 30, 2025
- Samsung Electronics Co., Ltd.
- Ju Seong MIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3T MEMORY WITH ENHANCED SPEED OF OPERATION AND DATA RETENTION
- Publication number 20250031380
- Publication date Jan 23, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Li Chiang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEUR...
- Publication number 20250029638
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Kamal M. Karda
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL NOR MEMORY DEVICE FOR MULTIPLY-ACCUMULATE OPERATIONS
- Publication number 20250029659
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Kamal Karda
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATION IN-MEMORY USING 6-TRANSISTOR BIT CELLS
- Publication number 20250029652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Avishek BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED POWER SUPPLY SWITCHING CIRCUIT FOR EFUSE MEMORY
- Publication number 20250029668
- Publication date Jan 23, 2025
- Shanghai Huali Integrated Circuit Corporation
- Chuyi HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVOLUTION OPERATION ACCELERATOR AND CONVOLUTION OPERATION METHOD
- Publication number 20250022490
- Publication date Jan 16, 2025
- HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
- Xiangshui MIAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE
- Publication number 20250024671
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien Hui Huang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF CHANNEL...
- Publication number 20250024685
- Publication date Jan 16, 2025
- Sunrise Memory Corporation
- Jie Zhou
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY DEVICES AND MEMORY PACKAGES INCLUDING THE SAME
- Publication number 20250014645
- Publication date Jan 9, 2025
- Samsung Electronics Co., Ltd.
- Minsu Kim
- G11 - INFORMATION STORAGE
Information Patent Application
READ-ONLY MEMORY METHOD, LAYOUT, AND DEVICE
- Publication number 20250014659
- Publication date Jan 9, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ku-Feng LIN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20250014643
- Publication date Jan 9, 2025
- KIOXIA Corporation
- Hiroshi MAEJIMA
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF M...
- Publication number 20250014614
- Publication date Jan 9, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Application
Storage Array, and Interconnection Structure and Method for Operati...
- Publication number 20250006228
- Publication date Jan 2, 2025
- ZHEJIANG HIKSTOR TECHNOLOGY CO., LTD.
- Kunkun LI
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20250006229
- Publication date Jan 2, 2025
- TOKYO ELECTRON LIMITED
- Motoyuki SATO
- G11 - INFORMATION STORAGE

Arrangements for interconnecting storage elements electrically

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Decoder architectures for three-dimensional memory devices

Chip bump interface compatible with different orientations and type...

Semiconductor device, memory device, and electronic device

Semiconductor device

Memory device including a word line with portions with different si...

Semiconductor memory device

Memory system

Fabrication method of buried wordline structure

Semiconductor memory device

Semiconductor device and method for fabricating the same

Semiconductor device having word line structure

Memory array connections

Methods for depositing a molybdenum nitride film on a surface of a...

Component inter-digitated vias and leads

Memory device and method of forming the same

Semiconductor device and method of manufacturing the same

Atomic compare and swap in a coherent cache system

Integrated assemblies having transistor body regions coupled to car...

Semiconductor wiring device and method

Control circuit on memory chip and dynamic random access memory

Techniques to manufacture ferroelectric memory devices

Aggressive write flush scheme for a victim cache

Semiconductor memory device having memory chip bonded to a CMOS chi...

Semiconductor storage device comprising a one-port SRAM cell formed...

Semiconductor storage device

Multi-die package

Memory device

Memory device having physical unclonable function and memory system...

Three-dimensional memory array with dual-level peripheral circuits...

Semiconductor memory device

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY DEVICES WITH CONDUCTIVE SPACERS

NAND String Utilizing Floating Body Memory Cell

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS AND METHOD FOR MANUFACT...

TERNARY CONTENT-ADDRESSABLE MEMORY CELLS AND METHODS FOR FORMING TH...

STRUCTURES OF SRAM CELL AND METHODS OF FABRICATING THE SAME

SEMICONDUCTOR DEVICE

DELAY OF INITIALIZATION AT MEMORY DIE

ARCHITECTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHODS REGARDI...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

Method for forming layout pattern of static random access memory

On-Die Termination of Address and Command Signals

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE

3T MEMORY WITH ENHANCED SPEED OF OPERATION AND DATA RETENTION

MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEUR...

THREE-DIMENSIONAL NOR MEMORY DEVICE FOR MULTIPLY-ACCUMULATE OPERATIONS

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

COMPUTATION IN-MEMORY USING 6-TRANSISTOR BIT CELLS

DISTRIBUTED POWER SUPPLY SWITCHING CIRCUIT FOR EFUSE MEMORY

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

CONVOLUTION OPERATION ACCELERATOR AND CONVOLUTION OPERATION METHOD

MEMORY DEVICE

MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF CHANNEL...

NONVOLATILE MEMORY DEVICES AND MEMORY PACKAGES INCLUDING THE SAME

READ-ONLY MEMORY METHOD, LAYOUT, AND DEVICE

MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF M...

Storage Array, and Interconnection Structure and Method for Operati...

SEMICONDUCTOR MEMORY DEVICE