Patent Application
20250218503
One embodiment of the present invention relates to a semiconductor device and the like.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Thus, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display apparatus, a light-emitting apparatus, a power storage device, a storage device (memory device), a driving method thereof, and a manufacturing method thereof.
A DRAM (Dynamic Random Access Memory) stores data by accumulation of charge in a capacitor. Thus, a lower off-state current of an access transistor for controlling the supply of charge to the capacitor is preferable, because the lower off-state current enables a longer data retention period and a lower frequency of refresh operation.
A transistor including a metal oxide semiconductor (preferably an oxide semiconductor containing In, Ga, and Zn) in its semiconductor layer is known as a kind of transistor. It is known that a transistor including a metal oxide in its semiconductor layer has an extremely low off-state current. Note that in this specification, a transistor including a metal oxide in its semiconductor layer is referred to as an oxide semiconductor transistor, a metal oxide transistor, an OS transistor, or the like in some cases.
The use of an OS transistor enables a semiconductor device having excellent data retention characteristics to be formed. For example, Patent Document 1 describes that a semiconductor device can be downsized by stacking a peripheral circuit and a cell array.
To achieve higher performance and lower power consumption of a computing system, a further reduction in power consumption, an increase in operating speed, downsizing, an increase in memory capacity, and the like, in a semiconductor device such as a DRAM are required.
An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device that is excellent in reducing power consumption, increasing operation speed, downsizing, or increasing memory capacity.
Note that the objects of one embodiment of the present invention are not limited to the objects listed above. The objects listed above do not preclude the existence of other objects. Note that the other objects are objects that are not described in this section and are described below. The objects that are not described in this section are derived from the description of the specification, the drawings, and the like and can be extracted as appropriate from the description by those skilled in the art. Note that one embodiment of the present invention is to achieve at least one of the above objects and the other objects.
One embodiment of the present invention is a semiconductor device including an arithmetic device, a bus wiring, and a memory device; the memory device includes a first element layer including a plurality of reading circuits and a second element layer including a plurality of cell arrays; the reading circuits each include a sense amplifier; the cell arrays each include a memory cell; the second element layer is provided to be over and overlap with the first element layer; the memory cell and the sense amplifier are electrically connected to each other through a bit line; the memory device is electrically connected to the arithmetic device through the bus wiring; and data retained in one of the plurality of cell arrays is output to the bus wiring through one of the plurality of reading circuits.
In the semiconductor device of one embodiment of the present invention, it is preferable that the data output to the bus wiring be output with a bit width that is a multiple of 8 bits.
In the semiconductor device of one embodiment of the present invention, it is preferable that the first element layer include an input/output circuit and the input/output circuit include a plurality of interface circuits.
In the semiconductor device of one embodiment of the present invention, it is preferable that the reading circuits each include a precharge circuit.
In the semiconductor device of one embodiment of the present invention, it is preferable that the first element layer include a first transistor in which a first semiconductor layer including a channel formation region includes silicon and the second element layer include a second transistor in which a second semiconductor layer including a channel formation region includes an oxide semiconductor.
In the semiconductor device of one embodiment of the present invention, the oxide semiconductor preferably includes In, Ga, and Zn.
In the semiconductor device of one embodiment of the present invention, the memory cell includes a capacitor and the second transistor; the capacitor includes a first conductor, a second conductor, a first insulator, and a second insulator; the second transistor includes the second conductor, a third conductor, a fourth conductor, a third insulator, a fourth insulator, and the second semiconductor layer; the first insulator includes a first opening; the first conductor is positioned on a side surface and a bottom surface of the first opening and a top surface of the first insulator; the second insulator is positioned on the top surface of the first insulator and a top surface and a side surface of the first conductor; the second conductor is positioned in a region of a top surface and a side surface of the second insulator that overlaps with the first conductor; the third insulator is positioned on a top surface of the second conductor; the third conductor is positioned on a top surface of the third insulator; the third insulator and the third conductor include a second opening; the second semiconductor layer is positioned on a side surface of the second opening, the top surface of the second conductor, and a top surface and a side surface of the third conductor; the fourth insulator is positioned on a top surface and a side surface of the second semiconductor layer and the top surface of the third conductor; and the fourth conductor is positioned in a region of a top surface and a side surface of the fourth insulator that overlaps with the second semiconductor layer.
Note that other embodiments of the present invention will be described in the following embodiments and the drawings.
One embodiment of the present invention can provide a novel semiconductor device or the like. Another embodiment of the present invention can provide a semiconductor device that is excellent in reducing power consumption, increasing operation speed, downsizing, or increasing memory capacity.
Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily need to have all these effects. Note that other effects will be apparent from the description of the specification, the drawings, the claims, and the like and other effects can be derived from the description of the specification, the drawings, the claims, and the like.
Embodiments will be described below with reference to the drawings. The embodiments can be implemented with various modes. It will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of embodiments below.
In the drawings, the size, the layer thickness, or the region is sometimes exaggerated for clarity. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings schematically show ideal examples, and the embodiment of the present invention is not limited to shapes or values shown in the drawings.
Unless otherwise specified, an off-state current in this specification and the like refers to a drain current of a transistor in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, an off state refers to, in an n-channel transistor, a state where a voltage Vgs between its gate and source is lower than a threshold voltage Vth (in a p-channel transistor, higher than Vth).
In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as OS), and the like. For example, a metal oxide used in an active layer of a transistor is referred to as an oxide semiconductor in some cases. That is, an OS transistor can also be referred to as a transistor including a metal oxide or an oxide semiconductor.
A semiconductor device described in one embodiment of the present invention functions as an SoC (System on Chip) in which the arithmetic device, the memory device, or the like inputs and outputs data through the bus wiring.
Note that in this specification, the drawings, and the like, an X direction, a Y direction, and a Z direction are sometimes defined to describe arrangement of components. For example, in the schematic view illustrated in
In the schematic view illustrated in
The memory device 10 includes an element layer 20 and an element layer 30. In the memory device 10, the element layer 30 is stacked over the element layer 20. The element layer and the element layer 30 are layers including elements such as transistors. When elements such as transistors are included, the memory device 10 enables the element layers to be provided with circuits with different functions.
The element layer 20 includes a transistor in which a semiconductor layer including a channel formation region includes silicon (a Si transistor). The element layer 20 is an element layer provided with a substrate containing silicon. The element layer 20 is referred to as a base die or a die in some cases.
It is preferable for the Si transistors to use silicon with high crystallinity such as single crystal silicon or polycrystalline silicon in order to achieve high field-effect mobility and perform a higher-speed operation.
The element layer 30 includes a transistor in which a semiconductor layer including a channel formation region includes oxide semiconductor (an OS transistor). The element layer 30 including the OS transistor can be stacked over the element layer 20 including the Si transistor. The element layer 30 is referred to as a die in some cases. In the memory device 10 illustrated in
Examples of a metal oxide used in the OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains two or three selected from indium, an element M, and zinc. Note that the element M is one or more kinds selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Specifically, the element M is preferably one or more kinds selected from aluminum, gallium, yttrium, and tin.
It is particularly preferable that an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) be used as the metal oxide. Alternatively, it is preferable to use an oxide containing indium, tin, and zinc (also referred to as ITZO). Further alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc. Further alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO). Further alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO). Further alternatively, it is preferable to use an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (also referred to as IGZTO).
The metal oxide used in the OS transistors may include two or more metal oxide layers with different compositions. For example, a stacked-layer structure of a first metal oxide layer having In: M:Zn=1:3:4 [atomic ratio] or a composition in the neighborhood thereof and a second metal oxide layer having In: M:Zn=1:1:1 [atomic ratio] or a composition in the neighborhood thereof and being formed over the first metal oxide layer can be suitably employed.
Alternatively, a stacked structure of one selected from indium oxide, indium gallium oxide, and IGZO, and one selected from IAZO, IAGZO, and ITZO may be employed, for example.
The metal oxide used in the OS transistors preferably has crystallinity. Examples of an oxide semiconductor having crystallinity include a CAAC (c-axis aligned crystalline)-OS and an nc (nanocrystalline)-OS. When the oxide semiconductor having crystallinity is used, the semiconductor device can have high reliability.
In the memory device 10, the element layer 20 and the element layer 30, or the circuits provided in the element layer 20 and the element layer 30 are collectively referred to as a memory block array 60. The memory block array 60 includes a plurality of memory blocks 61. The memory block 61 includes a cell array 31 including a plurality of memory cells 32 and a reading circuit 23 for reading data retained in the memory cells 32. The memory block 61 is composed of one set of the cell array 31 and the reading circuit 23.
The memory block 61 has a structure in which the cell array 31 and the reading circuit 23 are provided to overlap with each other. Note that in the case where the cell array 31 is referred to as a local cell array, the whole cell array composed of a plurality of cell arrays 31 is referred to as a memory cell array in some cases.
For example, the memory cell 32 is preferably a DOSRAM, which is a memory circuit including an OS transistor (also referred to as an OS memory). A DOSRAM (registered trademark) is an abbreviation for a “Dynamic Oxide Semiconductor Random Access Memory”. A DOSRAM refers to a RAM including a IT (transistor) 1C (capacitor) memory cell. A DOSRAM is a DRAM formed using an OS transistor, and a memory that temporarily stores information sent from the outside. A DOSRAM is a memory utilizing a low off-state current of an OS transistor.
In an OS transistor, a current that flows between a source and a drain in an off state, that is, an off-state current is extremely low. A DOSRAM can retain charge corresponding to data stored in a capacitor (also referred to as cell capacitance) for a long time by making an access transistor in an off state (by bringing the access transistor into a non-conducting state). For this reason, the refresh operation frequency of a DOSRAM can be lower than that of a DRAM formed using a Si transistor. As a result, power consumption can be reduced. Furthermore, a DOSRAM can be a memory cell that stores 1 bit data in a smaller occupation area than an SRAM formed using a Si transistor.
In addition, the memory cell 32 including an OS transistor can have a structure in which the cell array 31 is provided to overlap with the reading circuit 23; thus, the distance between the cell array 31 and the reading circuit 23 can be shortened. Therefore, power consumption needed for charge and discharge between wirings can be inhibited. When the cell array 31 is provided in each region that is to be the memory block 61, the number of the memory cells 32, which are electrically connected to the bit line, can be reduced. Thus, as well as the distance between the cell array 31 and the reading circuit 23, the number of memory cells 32 can be reduced, and the capacitance caused by the bit line (also referred to as bit line capacitance or load capacitance) can be reduced. By reducing the bit line capacitance, the capacitance included in the memory cell 32 can be designed to be small.
Although a DOSRAM is described as an example of the structure that can be used for the memory cell 32 in this embodiment, another structure may be employed as long as a cell array that can be stacked over the element layer 20 can be formed. For example, a NOSRAM that is a memory circuit including OS transistors may be used as well. NOSRAM (registered trademark) is an abbreviation for “Nonvolatile Oxide Semiconductor Random Access Memory (RAM)”. A memory cell in a NOSRAM is a two-transistor (2-T) or three-transistor (3T) gain cell.
Note that the transistors included in the memory cells 32 are all preferably OS transistors. In an OS transistor, a current that flows between a source and a drain in an off state, that is, an off-state current is extremely low. A NOSRAM can be used as a nonvolatile memory by retaining charge corresponding to data in the memory cell 32, using characteristics of extremely low off-state current. In particular, a NOSRAM is capable of reading retained data without destruction (non-destructive reading), and thus is suitable for arithmetic processing in which only a data reading operation is repeated many times.
The reading circuit 23 includes a precharge circuit 21 and a sense amplifier 22. The cell array 31 and the reading circuit 23 are electrically connected to each other with a bit line pair composed of a bit line BL and an inverted bit line BLB. The bit line BL and the inverted bit line BLB are simply referred to as wirings in some cases. Note that the bit line pair is a combination of the bit line and the inverted bit line that are compared simultaneously by the sense amplifier 22, and is sometimes referred to as a bit line pair (BL, BLB). Note that the sense amplifier 22 indicates a local sense amplifier in some cases. In this case, the whole sense amplifier composed of a plurality of sense amplifiers 22 is referred to as a sense amplifier array in some cases.
The reading circuit 23 is electrically connected to one bit line pair. The reading circuit 23 has a function of equilibration (an equalizer) in addition to a function of precharging a bit line pair.
The sense amplifier 22 is electrically connected to one bit line pair. The sense amplifier 22 has a function of amplifying the potential difference between the bit line pair (BL, BLB). In
The input/output circuit 50 has a function of delivering signals from/to an external device such as the bus wiring 200. The input/output circuit 50 includes a plurality of interface circuits. As an interface circuit, I2C, LVDS (Low-Voltage Differential Signaling), MIPI (Mobile Industry Processor Interface), SPI (Serial Peripheral Interface), or the like is given. The input/output circuit 50 has a function of delivering signals between an external device such as the bus wiring 200 and the memory device 10 through the interface circuit.
The control circuit 40 has a function of processing a setting parameter and a command signal from the outside and determining the operating mode of the memory device 10. The control circuit 40 has a function of generating a variety of control signals and controlling the operation of the whole memory device 10. Note that the control circuit 40 and the input/output circuit 50 included in the memory device 10 can be formed using the transistors and wirings included in the element layer 20 or the element layer 30.
The arithmetic device 300 includes an arithmetic portion 310 and an input/output circuit 309. The arithmetic device 300 has a function of performing general-purpose processing such as execution of an operating system, control of data, various kinds of arithmetic operations and an execution of programs, like a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). Like the input/output circuit 50, the input/output circuit 309 includes an interface circuit and has a function of delivering signals from/to an external device such as the bus wiring 200 through the interface circuit. The arithmetic portion 310 has a function of performing an arithmetic operation on the basis of input data. The arithmetic portion 310 is referred to as a CPU core in some cases.
The plurality of memory blocks 61 included in the memory device 10 described with reference to
In a schematic view illustrated in
8-bit data is read in parallel from the plurality of memory blocks 61. For example, as illustrated in
A structure different from that in
In a schematic view illustrated in
Data with a bit width of more than 64 bits cannot be output at a time to the bus wiring 200 having the 64-bit bit width at a time. Therefore, a structure in which reading from the plurality of memory blocks 61 is sequentially performed from the plurality of memory blocks 61 is preferably employed. For example, as illustrated in
A bit width of data output from the plurality of memory blocks 61 is preferably variable in accordance with the bit width of the bus wiring 200. For example, one memory block 61 employs a structure in which data with a bit width that is a multiple of 8 bits (a multiple of 1 byte) is output, and a bit width of data output is variable in accordance with the number of memory blocks 61 in parallel. In this case, data read from the memory device 10 can output data with a bit width that is a multiple of 8 bits, such as 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits, 512 bits, 1024 bits, or 2048 bits, with a standard, which can be processed by the arithmetic device 300. In other words, the memory device 10 can be used for a general-purpose DRAM with 64 bits or 128 bits or a high bandwidth memory (HBM), for example.
The bus width of the bus wiring 200 electrically connecting the memory device 10 and the arithmetic device 300 is determined by a standard or the like, and data is input and output at high speed through an interface circuit or the like. A bit width of data read from the plurality of memory blocks 61 is preferably set in accordance with the bit width of the bus wiring 200.
In the structure in which data with a large bit width can be output by increasing the parallel number of the memory blocks 61 in parallel, output of data between the memory device and the arithmetic device 300 through the bus wiring 200 is preferably performed at higher speed. For example, as illustrated in
In the case where data is output in accordance with the bit width of the bus wiring 200 in the memory block 61, the memory density per unit area is preferably increased. For example, as illustrated in a block diagram and a perspective view illustrated in
When the element layers 30_1 to 30_n are stacked, that is, the element layers 30 are stacked, the cell arrays 31 can be stacked. The stacked element layers 30 are provided in the direction perpendicular to the surface of the substrate provided with the element layer 20 (z direction), whereby the memory density of the memory cells 32 can be improved. Moreover, the element layers 30 can be formed by repeating the same manufacturing process in the vertical direction. The manufacturing cost of the element layer 30 in the memory device 10 can be reduced.
Note that in
Note that as the number of layers of the element layers 30_1 to 30_n increases, the load capacitance of the bit line increases. In this case, it is preferable to employ a structure in which an element layer including an amplifier circuit having a function of amplifying and outputting a potential difference of data retained in the memory cell 32 is included between the element layer including the sense amplifier 22 and the element layer 30 including the memory cell 32.
The transistor 33 is preferably an OS transistor having a back gate that is not illustrated in
The capacitor 34 has a function of retaining charge corresponding to data. Note that when the capacitor includes a ferroelectric material, the memory cell 32 can be used as a ferroelectric memory. For example, HfZrOx can be used as the ferroelectric material. Note that the term “HfZrOx” does not represent the stoichiometry of a hafnium atom, a zirconium atom, and an oxygen atom.
The structure illustrated in
The memory cell 32 shows a structure example of the DOSRAM illustrated in
Signals EQ, EQB, SEN, SENB, and CSEL and a voltage Vpre are input to the reading circuit 23. The signals EQB and SENB are inverted signals of the signals EQ and SEN, respectively. The transistors included in the reading circuit 23 are Si transistors. Thus, an n-channel transistor 25n and a p-channel transistor 25p can be employed.
The reading circuit 23 includes the precharge circuit 21 (also referred to as an equalizer), the sense amplifier 22, and a selector 24. The signals EQ and EQB are signals for activating the precharge circuit 21, and the signals SEN and SENB are signals for activating the sense amplifier 22. A signal CSEL is a signal for selecting whether to establish electrical continuity between any one of a plurality of bit line pairs and the global bit line pair (GBL, GBLB).
The reading circuit 23 illustrated in
When the length of the bit line pair (BL, BLB) is shortened, the bit line capacitance can be reduced. An index that affects reading performance is the ratio of the bit line capacitance (Cbit) to the capacitance Cs of the capacitor 34. With a higher Cs/Cbit, a larger potential difference of the bit line pair (BL, BLB) can be obtained when data is read from the memory cell 32. Therefore, a larger Cs/Cbit enables higher-speed or more stable reading operation. Under the condition where the reading performance is constant, a reduction in the bit line capacitance Cbit enables a reduction in the capacitance Cs of the capacitor 34. Therefore, in the case where the memory cell 32 is a DOSRAM and the capacitance Cs of the capacitor 34 is the same as the bit line capacitance Cbit, the memory cell 32 has excellent reading performance compared with a conventional DRAM using Si transistors.
In the case where the memory cell 32 is a DOSRAM, the OS transistor has an extremely low off-state current; thus, even when the capacitance Cs is smaller than that of a DRAM, the memory cell 32 has excellent retention characteristics compared with a conventional DRAM. Therefore, in the case where the memory cell 32 is a DOSRAM, the capacitance value of the capacitor of the memory cell can be smaller than the capacitance value of the capacitor of a DRAM, which is preferable.
In the circuit diagram in
Note that in
The adjacent cell arrays 31_A and 31_B and the adjacent reading circuits 23_A and 23_B can be arranged as illustrated in
In the case of the structure in
For example, as illustrated in
With this structure, data of the memory cell 32_A included in the cell array 31_A selected by any one of the word lines <0> to WL<7> can be separately output to a sense amplifier 22_A and a sense amplifier 22_B. Similarly, data of the memory cell 32_B included in the cell array 31_B selected by any one of the word lines <8> to WL<15> can be separately output to the sense amplifier 22_A and the sense amplifier 22_B. In the sense amplifier 22_A and the sense amplifier 22_B, the load capacitance of the bit line pair (BL_A, BLB_A) and the bit line pair (BL_B, BLB_B) can be made substantially the same by the wiring layers 70_A and 70_B. Thus, the load capacitance values of the bit line pairs (BL, BLB) can be close to the same as each other, and the density of memory cells per unit area can be increased.
In the memory device 10 illustrated in
The input/output circuit 50 has a function of delivering signals from/to an external device. Operation conditions and the like of the memory device 10 are determined by setting parameters stored in the setting register 42. The setting parameters are written into the setting register 42 through the input/output circuit 50 and the I2C receiver 41. Note that the I2C receiver 41 may be omitted depending on the purpose, the usage, or the like.
Examples of the setting parameters include designation information about execution intervals of refresh operations or timing of circuit operations, and the like. The control circuit 40 has a function of processing the setting parameters and a command signal from the outside and determining the operation mode of the memory device 10. The control circuit 40 has a function of generating a variety of control signals and controlling the operation of the whole memory device 10.
In addition, a reset signal res, an address signal ADDR, a row address identification signal RAS (Row Address Strobe), a column address identification signal CAS (Column Address Strobe) write data WDATA, and the like are supplied to the control circuit 40 from the outside through the input/output circuit 50. A clock signal for data writing is supplied to the control circuit through the LVDS circuit 43.
Read data RDATA is supplied from the control circuit 40 to the input/output circuit 50. A clock signal for data reading is supplied to the input/output circuit 50 through the LVDS circuit 44.
The write data WDATA is transmitted in synchronization with the clock signal for data writing and retained in the register 46 in the control circuit 40. The control circuit 40 has a function of supplying data W retained in the register 46 to the memory block array 60.
Data R read from the memory block array 60 is retained as the read data RDATA in the register 45 in the control circuit 40. The control circuit 40 has a function of transmitting the read data RDATA to the input/output circuit 50 in synchronization with the clock signal for data reading.
The control circuit 40 has a function of outputting a column address signal C_ADDR, a column selection enable signal CSEL_EN, a data latch signal DLAT, a global writing enable signal GW_EN, a global reading enable signal GR_EN, a global sense amplifier enable signal GSA_EN, a global equalization enable signal GEQ_ENB, a local sense amplifier enable signal LSA_EN, a local equalization enable signal LEQ_ENB, a word line address selection signal WL_ADDR, and the like.
The column address signal C_ADDR and the column selection enable signal CSEL_EN are supplied to the decoder 35.
The transistor 33 is an OS transistor. The off-state current of an OS transistor is extremely low. Thus, the memory cell 32 can reduce the frequency of data refresh. Therefore, power required for data retention can be reduced.
Since the write transistor is formed using an OS transistor, charge corresponding to data can be retained continuously by turning off the write transistor. Therefore, the memory cell 32A does not consume power for data retention. Thus, the memory cell 32A can function as a memory cell with low power consumption that can retain data for a long time.
Other structure examples of memory cells used for NOSRAMs are described with reference to
A memory cell 32B illustrated in
In the above-described gain cells, a bit line serving as both the wiring RBL and the wiring WBL may be provided.
In the case where the memory cell 32 is a DOSRAM or a NOSRAM, the wirings (the word lines WL and WWL in
A schematic cross-sectional view of an IC chip 11A illustrated in
In the case where a plurality of element layers 30_1 to 30_4 are stacked three-dimensionally as illustrated in
As another example, a schematic cross-sectional view of an IC chip 11B illustrated in
The schematic cross-sectional view of the IC chip 11B illustrated in
The intervals between the wirings provided together with the transistors 57 can be more miniaturized than those between through electrodes used for a TSV or a Cu—Cu direct bonding technique. Accordingly, in the structure of the IC chip 11B illustrated in
As another example,
An interposer 103 provided with a wiring for electrically connecting the memory device included in the IC chip 11B and the arithmetic device 300 is provided over the package substrate 101. The wiring provided in the interposer 103 can function as the bus wiring 200. In addition to the memory device 10, the element layer 20 and the element layer 30 included in the arithmetic device 300 are illustrated over the interposer 103. The element layer 20 and the element layer 30 include the transistors 59, which are Si transistors, or the transistors 57, which are OS transistors.
In the schematic view of the IC chip 11C illustrated in
In the structure example of the arithmetic device 300 illustrated in
This embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.
In this embodiment, structures of transistors that can be used for the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. With this structure, the design flexibility of a semiconductor device can be increased. In addition, providing transistors having different electrical characteristics to be stacked can increase the integration degree of the semiconductor device.
In
The transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 that is part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b each functioning as a source region or a drain region.
As illustrated in
Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.
A region of the semiconductor region 313 where a channel is formed, a region in the vicinity thereof, the low-resistance region 314a and the low-resistance region 314b each functioning as a source region or a drain region, and the like preferably include a semiconductor such as a silicon-based semiconductor, and preferably include single crystal silicon. Alternatively, the regions may be formed using a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A structure using silicon whose effective mass is controlled by applying stress to a crystal lattice and changing lattice spacing may be employed. Alternatively, the transistor 550 may be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, or the like.
The low-resistance region 314a and the low-resistance region 314b include an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, in addition to the semiconductor material used for the semiconductor region 313.
For the conductor 316 functioning as a gate electrode, it is possible to use a semiconductor material such as silicon containing the element that imparts n-type conductivity, such as arsenic or phosphorus, or the element that imparts p-type conductivity, such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material.
Note that since a work function depends on the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Moreover, in order to ensure both conductivity and embeddability, it is preferable to use stacked layers of metal materials such as tungsten and aluminum for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.
As the SOI substrate, any of the following substrates may be used: a SIMOX (Separation by Implanted Oxygen) substrate formed in such a manner that an oxygen ion is implanted into a mirror-polished wafer, and then, an oxide layer is formed at a certain depth from the surface and defects generated in a surface layer are eliminated by high-temperature annealing, and an SOI substrate formed by a Smart-Cut method in which a semiconductor substrate is cleaved by utilizing growth of a minute void, which is formed by implantation of a hydrogen ion, by heat treatment; an ELTRAN method (registered trademark: Epitaxial Layer Transfer); or the like. A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.
An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided to cover the transistor 550.
For the insulator 320, the insulator 322, the insulator 324, and the insulator 326, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used, for example.
Note that in this specification, silicon oxynitride refers to a material that has a higher oxygen content than a nitrogen content, and silicon nitride oxide refers to a material that has a higher nitrogen content than an oxygen content. Moreover, in this specification, aluminum oxynitride refers to a material that has a higher oxygen content than a nitrogen content, and aluminum nitride oxide refers to a material that has a higher nitrogen content than an oxygen content.
The insulator 322 may have a function of a planarization film for eliminating a level difference caused by the transistor 550 or the like provided therebelow. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to have improved planarity.
For the insulator 324, it is preferable to use a film having a barrier property that prevents diffusion of hydrogen, impurities, or the like from the substrate 311, the transistor 550, or the like into a region where the transistor 500 is provided.
For the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used, for example. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, degrades the characteristics of the semiconductor element in some cases. Thus, a film that inhibits hydrogen diffusion is preferably provided between the transistor 500 and the transistor 550. The film that inhibits hydrogen diffusion is specifically a film from which a small amount of hydrogen is released.
The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS) or the like, for example. The amount of hydrogen released from the insulator 324 that is converted into hydrogen atoms per area of the insulator 324 is less than or equal to 1×1016 atoms/cm2, preferably less than or equal to 5×1015 atoms/cm2, in TDS analysis in a film-surface temperature range of 50° C. to 500° C., for example.
Note that the permittivity of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably lower than 4, further preferably lower than 3. In addition, the relative permittivity of the insulator 326 is, for example, preferably 0.7 times or less, further preferably 0.6 times or less the relative permittivity of the insulator 324. When a material with low permittivity is used for the interlayer film, parasitic capacitance generated between wirings can be reduced.
A conductor 328, a conductor 330, and the like that are connected to the capacitor 600 or the transistor 500 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 each function as a plug or a wiring. A plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. In this specification and the like, a wiring and a plug connected to the wiring may be a single component. That is, part of a conductor functions as a wiring in some cases and part of a conductor functions as a plug in other cases.
As a material for each of the plugs and wirings (the conductor 328, the conductor 330, and the like), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.
A wiring layer may be provided over the insulator 326 and the conductor 330. For example, an insulator 350, an insulator 352, and an insulator 354 are stacked sequentially in
Note that for example, the insulator 350 is preferably formed using an insulator having a barrier property against hydrogen, like the insulator 324. Furthermore, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated with a barrier layer, so that hydrogen diffusion from the transistor 550 into the transistor 500 can be inhibited.
Note that for the conductor having a barrier property against hydrogen, tantalum nitride or the like is preferably used, for example. By stacking tantalum nitride and tungsten, which has high conductivity, diffusion of hydrogen from the transistor 550 can be inhibited while the conductivity as a wiring is ensured. In that case, a tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.
A wiring layer may be provided over the insulator 354 and the conductor 356. For example, an insulator 360, an insulator 362, and an insulator 364 are stacked sequentially in
Note that for example, the insulator 360 is preferably formed using an insulator having a barrier property against hydrogen, like the insulator 324. Furthermore, the conductor 366 preferably includes a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening portion of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated with a barrier layer, so that hydrogen diffusion from the transistor 550 into the transistor 500 can be inhibited.
A wiring layer may be provided over the insulator 364 and the conductor 366. For example, an insulator 370, an insulator 372, and an insulator 374 are stacked sequentially in
Note that for example, the insulator 370 is preferably formed using an insulator having a barrier property against hydrogen, like the insulator 324. Furthermore, the conductor 376 preferably includes a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated with a barrier layer, so that hydrogen diffusion from the transistor 550 into the transistor 500 can be inhibited.
A wiring layer may be provided over the insulator 374 and the conductor 376. For example, an insulator 380, an insulator 382, and an insulator 384 are stacked sequentially in
Note that for example, the insulator 380 is preferably formed using an insulator having a barrier property against hydrogen, like the insulator 324. Furthermore, the conductor 386 preferably includes a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated with a barrier layer, so that hydrogen diffusion from the transistor 550 into the transistor 500 can be inhibited.
Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above, the semiconductor device according to this embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or five or more.
An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked and provided over the insulator 384. A substance having a barrier property against oxygen, hydrogen, or the like is preferably used for any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516.
For example, for each of the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property that prevents diffusion of hydrogen, impurities, or the like from the substrate 311, a region where the transistor 550 is provided, or the like into a region where the transistor 500 is provided. Thus, a material similar to that for the insulator 324 can be used.
For the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used, for example. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, degrades the characteristics of the semiconductor element in some cases. Thus, a film that inhibits hydrogen diffusion is preferably provided between the transistor 500 and the transistor 550. The film that inhibits hydrogen diffusion is specifically a film from which a small amount of hydrogen is released.
For the film having a barrier property against hydrogen used for each of the insulator 510 and the insulator 514, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.
In particular, aluminum oxide has an excellent blocking effect that prevents permeation of both oxygen and impurities such as hydrogen and moisture that cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as hydrogen and moisture into the transistor 500 during and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide contained in the transistor 500 can be prevented. Therefore, aluminum oxide is suitably used for a protective film of the transistor 500.
The insulator 512 and the insulator 516 can be formed using a material similar to that for the insulator 320, for example. In the case where a material with a relatively low permittivity is used for these insulators, the parasitic capacitance between wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 512 and the insulator 516, for example.
A conductor 518, a conductor included in the transistor 500 (e.g., a conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring that is connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that for the conductor 328 and the conductor 330.
In particular, the conductor 518 in a region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. In such a structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, so that the hydrogen diffusion from the transistor 550 into the transistor 500 can be inhibited.
The transistor 500 is provided over the insulator 516.
As illustrated in
In addition, as illustrated in
In this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as an oxide 530.
Although the transistor 500 having, in the region where the channel is formed and its vicinity, a structure in which two layers of the oxide 530a and the oxide 530b are stacked is described, the present invention is not limited thereto. For example, a single layer structure of the oxide 530b or a stacked-layer structure of three or more layers may be provided.
Although the conductor 560 has a stacked-layer structure of two layers in the transistor 500, the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked-layer structure of three or more layers. Furthermore, the transistor 500 illustrated in
Here, the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode and a drain electrode. As described above, the conductor 560 is embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The positions of the conductor 560, the conductor 542a, and the conductor 542b with respect to the opening of the insulator 580 are selected in a self-aligned manner. That is, in the transistor 500, the gate electrode can be positioned between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without an alignment margin, resulting in a reduction in the area occupied by the transistor 500. Accordingly, miniaturization and high integration of the semiconductor device can be achieved.
Since the conductor 560 is formed in the region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thus, parasitic capacitance formed between the conductor 560 and each of the conductor 542a and the conductor 542b can be reduced. As a result, the transistor 500 can have increased switching speed and excellent frequency characteristics.
The conductor 560 functions as a first gate (also referred to as a top gate) electrode in some cases. The conductor 503 functions as a second gate (also referred to as a bottom gate) electrode in some cases. In that case, by changing a potential applied to the conductor 503 independently of a potential applied to the conductor 560, the threshold voltage of the transistor 500 can be controlled. In particular, when a negative potential is applied to the conductor 503, the threshold voltage of the transistor 500 can be higher than 0 V, and the off-state current can be reduced. Thus, a drain current when a potential applied to the conductor 560 is 0 V can be smaller in the case where a negative potential is applied to the conductor 503 than in the case where the negative potential is not applied to the conductor 503.
The conductor 503 is positioned to overlap with the oxide 530 and the conductor 560. Accordingly, in the case where potentials are applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected, thereby covering the channel formation region in the oxide 530.
In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by the electric field of a first gate electrode is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification and the like is different from a Fin structure or a planar structure. The S-channel structure disclosed in this specification and the like can be regarded as a kind of the Fin structure. In this specification and the like, the Fin structure refers to a structure in which at least two surfaces (specifically, two surfaces, three surfaces, four surfaces, or the like) of a channel are covered with a gate electrode. With the use of the Fin structure or the S-channel structure, a transistor with high resistance to a short-channel effect, i.e., a transistor in which a short-channel effect is unlikely to occur, can be obtained.
When the transistor has the above-described S-channel structure, the channel formation region can be electrically surrounded. Since the S-channel structure is a structure with the electrically surrounded channel formation region, the S-channel structure is, in a sense, equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. In the transistor having any of the S-channel structure, the GAA structure, and the LGAA structure, the channel formation region that is formed at the interface between the oxide 530 and the gate insulator or in the vicinity of the interface can be the entire bulk of the oxide 530. Consequently, the density of current flowing through the transistor can be improved, so that the on-state current or the field-effect mobility of the transistor can be expected to increase.
The conductor 503 has a structure similar to that of the conductor 518; a conductor 503a is formed in contact with an inner wall of the opening in the insulator 514 and the insulator 516, and a conductor 503b is formed on the inner side. Although the transistor 500 having a structure in which the conductor 503a and the conductor 503b are stacked is described, the present invention is not limited thereto. For example, the conductor 503 may have a single-layer structure or a stacked-layer structure of three or more layers.
The conductor 503a is preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom (a conductive material through which the above impurities are less likely to pass). Alternatively, the conductor 503a is preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (a conductive material through which the above oxygen is less likely to pass). Note that in this specification, a function of inhibiting diffusion of impurities or oxygen means a function of inhibiting diffusion of any one or all of the above impurities and the above oxygen.
For example, when the conductor 503a has a function of inhibiting diffusion of oxygen, the conductivity of the conductor 503b can be prevented from being lowered because of oxidation.
In the case where the conductor 503 also functions as a wiring, the conductor 503b is preferably formed using a conductive material with high conductivity that contains tungsten, copper, or aluminum as its main component. Although the conductor 503 has a stacked layer of the conductor 503a and the conductor 503b in this embodiment, the conductor 503 may have a single-layer structure.
The insulator 520, the insulator 522, and the insulator 524 function as a second gate insulating film.
Here, an insulator containing oxygen more than that in the stoichiometric composition is preferably used as the insulator 524 in contact with the oxide 530. Such oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating is sometimes referred to as “excess oxygen”. That is, a region containing excess oxygen (also referred to as an “excess-oxygen region”) is preferably formed in the insulator 524. When such an insulator containing excess oxygen is provided in contact with the oxide 530, oxygen vacancies (also referred to as Vo) in the oxide 530 can be reduced, leading to an improvement in reliability of the transistor 500. When hydrogen enters the oxygen vacancies in the oxide 530, such defects (hereinafter, referred to as VoH in some cases) serve as donors and generate electrons serving as carriers in some cases. In other cases, bonding of part of hydrogen to oxygen bonded to a metal atom generates electrons serving as carriers. Thus, a transistor including an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics. Moreover, hydrogen in an oxide semiconductor is easily transferred by a stress such as heat or an electric field; thus, a large amount of hydrogen in an oxide semiconductor might reduce the reliability of a transistor. In one embodiment of the present invention, VoH in the oxide 530 is preferably reduced as much as possible so that the oxide 530 becomes a highly purified intrinsic or substantially highly purified intrinsic oxide. In order to obtain such an oxide semiconductor with sufficiently reduced VoH, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (this treatment is also referred to as “dehydration” or “dehydrogenation treatment”) and supply oxygen to the oxide semiconductor to fill oxygen vacancies (this treatment is also referred to as “oxygen adding treatment”). When an oxide semiconductor with a sufficiently reduced amount of impurities such as VoH is used for the channel formation region of the transistor, the transistor can have stable electrical characteristics.
As the insulator including the excess-oxygen region, specifically, an oxide material that releases part of oxygen by heating is preferably used. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018 atoms/cm3, preferably greater than or equal to 1.0×1019 atoms/cm3, further preferably greater than or equal to 2.0×1019 atoms/cm3 or greater than or equal to 3.0×1020 atoms/cm3 in TDS (Thermal Desorption Spectroscopy) analysis. In the TDS analysis, the film-surface temperature is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 400° C.
One or more of heat treatment, microwave treatment, and RF treatment may be performed in a state in which the insulator including the excess-oxygen region and the oxide 530 are in contact with each other. By the treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, dehydrogenation can be performed when a reaction in which a bond of VoH is cut occurs, i.e., a reaction of “VoH→Vo+H” occurs. Part of hydrogen generated at this time is bonded to oxygen to be H2O, and is removed from the oxide 530 or an insulator in the vicinity of the oxide 530 in some cases. Some hydrogen may be gettered into the conductors 542a and 542b in some cases.
For the microwave treatment, for example, an apparatus including a power supply that generates high-density plasma or an apparatus including a power supply that applies RF to the substrate side is suitably used. For example, the use of an oxygen-containing gas and high-density plasma enables high-density oxygen radicals to be generated, and application of the RF to the substrate side allows the oxygen radicals generated by the high-density plasma to be efficiently introduced into the oxide 530 or an insulator in the vicinity of the oxide 530. The microwave treatment is performed under a pressure of 133 Pa or higher, preferably 200 Pa or higher, further preferably 400 Pa or higher. As a gas introduced into an apparatus for performing the microwave treatment, for example, oxygen and argon are used and the oxygen flow rate ratio (O2/(O2+Ar)) is lower than or equal to 50%, preferably higher than or equal to 10% and lower than or equal to 30%.
In a manufacturing process of the transistor 500, the heat treatment is preferably performed with the surface of the oxide 530 exposed. For example, the heat treatment is performed at a temperature higher than or equal to 100° C. and lower than or equal to 450° C., preferably higher than or equal to 350° C. and lower than or equal to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at higher than or equal to 10 ppm, higher than or equal to 1%, or higher than or equal to 10%. For example, the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (Vo). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen gas atmosphere or an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, and then another heat treatment is successively performed in a nitrogen gas atmosphere or an inert gas atmosphere.
Note that the oxygen adding treatment performed on the oxide 530 can promote a reaction in which oxygen vacancies in the oxide 530 are filled with supplied oxygen, i.e., a reaction of “Vo+O→null”. Furthermore, hydrogen remaining in the oxide 530 reacts with supplied oxygen, so that the hydrogen can be removed as H2O (dehydration). This can inhibit recombination of hydrogen remaining in the oxide 530 with oxygen vacancies and formation of VoH.
In the case where the insulator 524 includes an excess-oxygen region, the insulator 522 preferably has a function of inhibiting diffusion of oxygen (e.g., oxygen atoms and oxygen molecules) (it is preferable that oxygen be less likely to pass through the insulator 522).
The insulator 522 preferably has a function of inhibiting diffusion of oxygen, impurities, or the like, in which case diffusion of oxygen contained in the oxide 530 to the insulator 520 side is prevented. In addition, the conductor 503 can be inhibited from reacting with oxygen in the insulator 524, the oxide 530, or the like.
The insulator 522 preferably has a single-layer structure or a stacked-layer structure using an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST), for example. With miniaturization and high integration of a transistor, a problem such as generation of an off-state current sometimes arises because of a thin gate insulating film. When a high-k material is used for an insulator functioning as the gate insulating film, a gate potential at the time of operating the transistor can be reduced while the physical thickness of the gate insulating film is kept.
It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material having a function of inhibiting diffusion of impurities, oxygen, and the like (an insulating material through which the above oxygen is less likely to pass). Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. The insulator 522 formed of such a material functions as a layer that inhibits release of oxygen from the oxide 530 or entry of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.
Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.
It is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are preferred because of their thermal stability. Furthermore, combination of an insulator which is a high-k material and silicon oxide or silicon oxynitride enables the insulator 520 to have a stacked-layer structure that is thermally stable and has a high relative permittivity.
Note that in the transistor 500 in
In the transistor 500, a metal oxide functioning as an oxide semiconductor is used as the oxide 530 including a channel formation region.
The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.
The metal oxide functioning as the channel formation region in the oxide 530 has a band gap of 2 eV or more, preferably 2.5 eV or more. The use of a metal oxide having such a wide band gap can reduce the off-state current of a transistor.
When the oxide 530a is provided below the oxide 530b in the oxide 530, impurities can be inhibited from diffusing into the oxide 530b from the components formed below the oxide 530a.
The oxide 530 preferably has a structure including a plurality of oxide layers that differ in the atomic ratio of metal atoms. Specifically, the atomic ratio of an element M to constituent elements in the metal oxide used as the oxide 530a is preferably greater than that in the metal oxide used as the oxide 530b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide 530a is preferably greater than that in the metal oxide used as the oxide 530b. Moreover, the atomic ratio of In to the element M in the metal oxide used as the oxide 530b is preferably greater than that in the metal oxide used as the oxide 530a.
The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.
Here, the energy level of the conduction band minimum gradually changes at a junction portion of the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at a junction portion of the oxide 530a and the oxide 530b is continuously varied or continuously connected. To change the energy level gradually, the density of defect states in a mixed layer formed at the interface between the oxide 530a and the oxide 530b is preferably made low.
Specifically, when the oxide 530a and the oxide 530b contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide 530b is an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as the oxide 530a.
At this time, the oxide 530b serves as a main carrier path. When the oxide 530a has the above structure, the density of defect states at the interface between the oxide 530a and the oxide 530b can be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor 500 can have a high on-state current.
The conductor 542a and the conductor 542b functioning as the source electrode and the drain electrode are provided over the oxide 530b. For the conductor 542a and the conductor 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements as its component; an alloy containing a combination of the above metal elements; or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are conductive materials that are less likely to be oxidized or materials that maintain their conductivity even after absorbing oxygen. Furthermore, a metal nitride film such as a tantalum nitride film is preferable because it has a barrier property against hydrogen or oxygen.
In addition, although the conductor 542a and the conductor 542b each having a single-layer structure are illustrated in
Other examples include a three-layer structure of a titanium film or a titanium nitride film, an aluminum film or a copper film stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride formed thereover and a three-layer structure of a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film formed thereover. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
In addition, as illustrated in
When the conductor 542a (the conductor 542b) is provided in contact with the oxide 530, the oxygen concentration in the region 543a (the region 543b) sometimes decrease. In addition, a metal compound layer that contains the metal contained in the conductor 542a (the conductor 542b) and the component of the oxide 530 is sometimes formed in the region 543a (the region 543b). In such cases, the carrier concentration of the region 543a (the region 543b) increases, and the region 543a (the region 543b) becomes a low-resistance region.
The insulator 544 is provided to cover the conductor 542a and the conductor 542b and inhibits oxidation of the conductor 542a and the conductor 542b. Here, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.
A metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, and the like can be used as the insulator 544. For the insulator 544, silicon nitride oxide or silicon nitride can be also used, for example.
It is particularly preferable to use, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like that is an insulator containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, hafnium aluminate is preferable because it is less likely to be crystallized by heat treatment in a later step. Note that the insulator 544 is not necessarily provided when the conductor 542a and the conductor 542b are oxidation-resistant materials or materials that do not significantly lose the conductivity even after absorbing oxygen. Design is determined as appropriate in consideration of required transistor characteristics.
The insulator 544 can inhibit impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. Moreover, the oxidation of the conductor 542a and 542b due to excess oxygen contained in the insulator 580 can be inhibited.
The insulator 545 functions as a first gate insulating film. The insulator 545 is preferably formed using an insulator which contains excess oxygen and from which oxygen is released by heating, like the insulator 524.
Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable.
When an insulator containing excess oxygen is provided as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. As in the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
Furthermore, in order that excess oxygen contained in the insulator 545 can be efficiently supplied to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably inhibits diffusion of oxygen from the insulator 545 into the conductor 560. Providing the metal oxide that inhibits diffusion of oxygen inhibits diffusion of excess oxygen from the insulator 545 into the conductor 560. That is, a reduction in the amount of excess oxygen supplied to the oxide 530 can be inhibited. Moreover, oxidation of the conductor 560 due to excess oxygen can be inhibited. For the metal oxide, a material that can be used for the insulator 544 is used.
Note that the insulator 545 may have a stacked-layer structure like the second gate insulating film. As miniaturization and high integration of transistors progress, a problem such as an off-state current might arise because of a thinner gate insulating film. For that reason, when the insulator functioning as the gate insulating film has a stacked-layer structure of a high-k material and a thermally stable material, a gate potential during transistor operation can be reduced while the physical thickness is maintained. Furthermore, the stacked-layer structure can be thermally stable and have a high relative permittivity.
Although the conductor 560 that functions as the first gate electrode and has a two-layer structure is illustrated in
The conductor 560a is preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). When the conductor 560a has a function of inhibiting diffusion of oxygen, the conductivity of the conductor 560b can be prevented from being lowered because of oxidation due to oxygen contained in the insulator 545. As a conductive material having a function of inhibiting diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. For the conductor 560a, the oxide semiconductor that can be used as the oxide 530 can be used. In that case, when the conductor 560b is formed by a sputtering method, the conductor 560a can have a reduced electrical resistance value to be a conductor. Such a conductor can be referred to as an OC (Oxide Conductor) electrode.
Furthermore, the conductor 560b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. In addition, the conductor 560b also functions as a wiring and thus a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor 560b may have a stacked-layer structure, for example, a stacked-layer structure of titanium or titanium nitride and any of the above conductive materials.
The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 therebetween. The insulator 580 preferably includes an excess-oxygen region. For example, the insulator 580 preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Silicon oxide and porous silicon oxide are particularly preferable because an excess-oxygen region can be formed easily in a later step.
The insulator 580 preferably includes an excess-oxygen region. When the insulator 580 that releases oxygen by heating is provided, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.
The opening of the insulator 580 is formed to overlap with a region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
The gate length needs to be short for miniaturization of the semiconductor device, but it is necessary to prevent a reduction in conductivity of the conductor 560. When the conductor 560 is made thick to achieve this, the conductor 560 might have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided to be embedded in the opening of the insulator 580; thus, even when the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.
The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. When the insulator 574 is deposited by a sputtering method, excess-oxygen regions can be provided in the insulator 545 and the insulator 580. Therefore, oxygen can be supplied from the excess-oxygen regions to the oxide 530.
For example, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used as the insulator 574.
In particular, aluminum oxide has a high barrier property, and even a thin aluminum oxide film having a thickness greater than or equal to 0.5 nm and less than or equal to 3.0 nm can inhibit diffusion of hydrogen and nitrogen. Thus, aluminum oxide deposited by a sputtering method can serve as not only an oxygen supply source but also a barrier film against impurities such as hydrogen.
An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. As in the insulator 524 or the like, the concentration of impurities such as water or hydrogen in the insulator 581 is preferably reduced.
A conductor 540a and a conductor 540b are provided in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided to face each other with the conductor 560 therebetween. The conductor 540a and the conductor 540b have a structure similar to that of a conductor 546 and a conductor 548 described later.
An insulator 582 is provided over the insulator 581. A material having a barrier property against oxygen, hydrogen, or the like is preferably used for the insulator 582. Thus, the insulator 582 can be formed using a material similar to that for the insulator 514. For the insulator 582, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used, for example.
In particular, aluminum oxide has an excellent blocking effect that prevents permeation of both oxygen and impurities such as hydrogen and moisture that cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as hydrogen and moisture into the transistor 500 during and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide contained in the transistor 500 can be prevented. Therefore, aluminum oxide is suitably used for a protective film of the transistor 500.
An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that for the insulator 320. In the case where a material with a relatively low permittivity is used for these insulators, the parasitic capacitance generated between wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used for the insulator 586, for example.
The conductor 546, the conductor 548, and the like are embedded in the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586.
The conductor 546 and the conductor 548 function as plugs or wirings that are connected to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that for the conductor 328 and the conductor 330.
After the transistor 500 is formed, an opening may be formed to surround the transistor 500 and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. Surrounding the transistor 500 by the insulator having a high barrier property can prevent entry of moisture and hydrogen from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by the insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, the formation of an opening reaching the insulator 522 or the insulator 514 and the formation of the insulator having a high barrier property in contact with the insulator 522 or the insulator 514 are suitable because these formation steps can also serve as some of the manufacturing steps of the transistor 500. The insulator having a high barrier property against hydrogen or water is formed using a material similar to that for the insulator 522 or the insulator 514, for example.
Note that the transistor that can be used in the present invention is not limited to the transistor 500 illustrated in
The conductor 542a has a stacked structure of the conductor 542al and the conductor 542a2 over the conductor 542al, and the conductor 542b has a stacked structure of the conductor 542b1 and the conductor 542b2 over the conductor 542b1. The conductor 542al and the conductor 542b1 in contact with the oxide 530b are preferably conductors that are less likely to be oxidized, such as metal nitride. In that case, the conductor 542a and the conductor 542b can be prevented from being oxidized excessively due to oxygen contained in the oxide 530b. The conductor 542a2 and the conductor 542b2 are preferably conductors having higher conductivity than the conductor 542al and the conductor 542b1, such as a metal layer. Accordingly, the conductor 542a and the conductor 542b can each function as a wiring or an electrode having high conductivity. In this manner, a semiconductor device in which the conductor 542a and the conductor 542b each function as a wiring or an electrode are provided in contact with the top surface of the oxide 530 functioning as an active layer can be provided.
As the conductors 542al and 542b1, a metal nitride is preferably used; for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. As another example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are each a conductive material that is less likely to be oxidized or a material that maintains the conductivity even after absorbing oxygen.
The conductor 542a2 and the conductor 542b2 preferably have higher conductivity than the conductor 542al and the conductor 542b1. For example, the thicknesses of the conductor 542a2 and the conductor 542b2 are preferably larger than the thicknesses of the conductor 542al and the conductor 542b1. As the conductor 542a2 and the conductor 542b2, a conductor that can be used as the conductor 560b can be used. The above structure can reduce the resistance of the conductor 542a2 and the conductor 542b2.
For example, tantalum nitride or titanium nitride can be used for the conductor 542al and the conductor 542b1, and tungsten can be used for the conductor 542a2 and the conductor 542b2.
As illustrated in
The insulator 555 is preferably an insulator that is less likely to be oxidized, such as nitride. The insulator 555 is formed in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2 and has a function of protecting the conductor 542a2 and the conductor 542b2. The insulator 555 is preferably an inorganic insulator that is less likely to be oxidized because it is exposed to an oxidation atmosphere. Since the insulator 555 is in contact with the conductor 542a2 and the conductor 542b2, the insulator 555 is preferably an inorganic insulator that is less likely to oxidize the conductors 542a2 and 542b2. Therefore, for the insulator 555, an insulating material having a barrier property against oxygen is preferably used. For the insulator 555, silicon oxynitride can be used.
The transistor 500 illustrated in
Heat treatment in an atmosphere containing oxygen is preferably performed after the separation of the conductor 542al and the conductor 542b1 and before the formation of the insulator 545. Accordingly, oxygen can be supplied to the oxide 530a and the oxide 530b to reduce oxygen vacancies. Furthermore, since the insulator 555 is formed in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2, excessive oxidation of the conductor 542a2 and the conductor 542b2 can be prevented. Accordingly, the transistor can have improved electrical characteristics and reliability. In addition, variations in electrical characteristics of transistors formed over the same substrate can be reduced.
In the transistor 500, the insulator 524 may be formed into an island shape, as illustrated in
In the transistor 500, the insulator 522 may be in contact with the insulator 516 and the conductor 503, as illustrated in
The capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.
A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring that is connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The conductor 612 and the conductor 610 can be formed at the same time.
The conductor 612 and the conductor 610 can be formed using a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like. Alternatively, it is possible to use a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.
Although the conductor 612 and the conductor 610 each having a single-layer structure are described in this embodiment, the structure is not limited thereto; a stacked-layer structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor that is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.
The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 620 is formed concurrently with another component such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low-resistance metal material, may be used.
An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be formed using a material similar to that for the insulator 320. In addition, the insulator 640 may function as a planarization film that covers an uneven shape thereunder.
With the use of the structure, a semiconductor device that includes a transistor including an oxide semiconductor can be miniaturized or highly integrated.
As a substrate that can be used for the semiconductor device of one embodiment of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, or the like), a semiconductor substrate (e.g., a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate, or the like), an SOI (Silicon on Insulator) substrate, or the like can be used. Alternatively, a plastic substrate having heat resistance to the processing temperature in this embodiment may be used. Examples of a glass substrate include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda lime glass. Alternatively, crystallized glass or the like can be used.
Alternatively, a flexible substrate, an attachment film, paper or a base film including a fibrous material, or the like can be used as the substrate. As examples of the flexible substrate, the attachment film, the base material film, and the like, the following can be given. Examples include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Alternatively, polyamide, polyimide, an aramid resin, an epoxy resin, an inorganic vapor deposition film, and paper can be used. Specifically, the use of a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like enables the manufacture of small-sized transistors with a small variation in characteristics, size, shape, or the like and with high current capability. A circuit using such transistors achieves lower power consumption or higher integration.
A flexible substrate may be used as the substrate, and a transistor, a resistor, a capacitor, and/or the like may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor, the resistor, the capacitor, and/or the like. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate and transferred to another substrate. In such a case, the transistor, the resistor, the capacitor, and/or the like can be transferred to a substrate having low heat resistance, a flexible substrate, or the like. Note that as the separation layer, a stacked-layer structure of a tungsten film and a silicon oxide film that are inorganic films, a structure in which an organic resin film of polyimide or the like is formed over a substrate, a silicon film containing hydrogen, or the like can be used, for example.
That is, a semiconductor device may be formed over one substrate and then transferred to another substrate. Examples of a substrate to which a semiconductor device is transferred include, in addition to the above-described substrates over which transistors can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupro, rayon, or regenerated polyester), or the like), a leather substrate, and a rubber substrate. With the use of any of these substrates, a flexible semiconductor device or a highly durable semiconductor device can be manufactured, high heat resistance can be provided, or a reduction in weight or thickness can be achieved.
Providing a semiconductor device over a flexible substrate can inhibit an increase in weight and allows the provided semiconductor device to be robust.
Note that the transistor 550 illustrated in
The configuration, structure, method, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in the other embodiments, examples, and the like.
In this embodiment, a cross-sectional structure example of stacked element layers that include OS transistors and can be used for a memory device or the like is described. In this embodiment, an example of a schematic cross-sectional view that can be used for a circuit structure such as a DOSRAM or a NOSRAM is described.
The transistor 550 illustrated in
A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the element layer 701 and the element layer 700 or between a k-th element layer 700 and a k+1-th element layer 700. In this embodiment and the like, the k-th element layer 700 is referred to as an element layer 700[k], and the k+1-th element layer 700 is referred to as an element layer 700[k+1], in some cases. Here, k is an integer greater than or equal to 1 and less than or equal to N. In this embodiment and the like, the solutions of “k+α (α is an integer greater than or equal to 1)” and “k-α” are each an integer greater than or equal to 1 and less than or equal to N.
A plurality of wiring layers can be provided in accordance with design. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, part of a conductor functions as a wiring in some cases, and part of a conductor functions as a plug in other cases.
For example, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are stacked in this order over the transistor 550 as interlayer films. The conductor 328 or the like is embedded in the insulator 320 and the insulator 322. The conductor 330 or the like is embedded in the insulator 324 and the insulator 326. Note that the conductor 328 and the conductor 330 each function as a contact plug or a wiring.
The insulator functioning as an interlayer film may also function as a planarization film that covers an uneven shape thereunder. For example, the top surface of the insulator 320 may be planarized by planarization treatment using a CMP method or the like to improve planarity.
A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in
Over the insulator 354, the insulator 514 included in the element layer 700[1] is provided. A conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 functions as a contact plug or a wiring. For example, the bit line BL and the transistor 550 are electrically connected to each other through the conductor 358, the conductor 356, the conductor 330, and the like.
The memory cell MC illustrated in
In this embodiment, a modification example of the transistor 500 is described as the transistor M1. Specifically, the transistor M1 is different from the transistor 500 in that the conductor 542a and the conductor 542b extend beyond the end portion of a metal oxide 531 (a metal oxide 531a and a metal oxide 531b).
The memory cell MC illustrated in
The capacitor C is formed in an opening portion that is provided by removal of part of the insulator 574, part of the insulator 580, and part of an insulator 554. The conductor 156, the insulator 580, and the insulator 554 are formed along the side surface of the opening portion, and thus are preferably deposited by an ALD method, a CVD method, or the like.
The conductor 156 and the conductor 160 may be formed using a conductor that can be used for a conductor 505 or the conductor 560. For example, the conductor 156 may be formed using titanium nitride by an ALD method. The conductor 160a may be formed using titanium nitride by an ALD method, and the conductor 160b may be formed using tungsten by a CVD method. Note that in the case where the adhesion of tungsten to the insulator 153 is sufficiently high, a single-layer film of tungsten formed by a CVD method may be used as the conductor 160.
As the insulator 153, an insulator of a high permittivity (high-k) material (material with a high relative permittivity) is preferably used. As the insulator of a high permittivity material, an oxide, an oxynitride, a nitride oxide, or a nitride containing one or more kinds of metal element selected from aluminum, hafnium, zirconium, gallium, and the like can be used, for example. The above-described oxide, oxynitride, nitride oxide, or nitride may include silicon. Insulating layers each formed of any of the above-described materials can be stacked to be used. As the insulator 153, a stacked-layer structure of three layers of zirconium oxide, aluminum oxide, and zirconium oxide is given for example. Note that the stacked-layer structure of the three layers may be referred to as ZrOxa\AlOxb\ZrOxc(ZAZ). Note that xa, xb, and xc described above are each a given unit.
As the insulator of high permittivity material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, an oxynitride containing hafnium and zirconium, or the like can be used, for example. Using such a high permittivity material allows the insulator 153 to be thick enough to inhibit an off-state current and a sufficiently high capacitance of the capacitor C to be ensured.
It is preferable to use stacked insulating layers each formed of any of the above-described materials. A stacked-layer structure using a high permittivity material and a material having higher dielectric strength than the high permittivity material is preferably used. For example, as the insulator 153, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Alternatively for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Alternatively for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in this order can be used. The use of stacked insulators with relatively high dielectric strength, such as aluminum oxide, can increase the dielectric strength and inhibit electrostatic breakdown of the capacitor C.
The memory cell MC illustrated in
The transistor M2 and the transistor M3 illustrated in
In the memory cell MC illustrated in
In
Next,
In
A conductor 363a, a conductor 363b, and a conductor 363c are embedded in an interlayer film between the element layer 701 and the element layer 700. In each of the plurality of element layers 700, a conductor 365 is embedded in an insulator 592 described later. Also, in each of the plurality of element layers 700, the conductor 366 is embedded in an insulator 593, an insulator 594, an insulator 553, and an insulator 595 that are described later. Furthermore, in each of the plurality of element layers 700, a conductor 367 is embedded in an insulator 596, an insulator 583, the conductor 542b, the insulator 555, and an insulator 597 that are described later. The conductor 363a, the conductor 363b, the conductor 363c, the conductor 365, the conductor 366, and the conductor 367 each function as a via hole, a contact plug, or a wiring.
Next, a structure example of the memory cell MC included in each of the plurality of element layers 700 of the memory device 10V in
The capacitor 600A includes the insulator 593, the insulator 594, the insulator 553, the insulator 595, a conductor 563, a conductor 564, and the conductor 542a, for example.
The conductor 563 is embedded in the insulator 592. The conductor 563 can be, for example, the wiring PL extending in the Y direction.
The insulator 593 and the insulator 594 are formed in this order over the insulator 592 and the conductor 563, for example. An opening is provided in a region of the insulator 593 and the insulator 594 that overlaps with the conductor 563. The conductor 564 is formed on the bottom surface of the opening (over the conductor 563) and the side surface of the opening. Note that in
The conductor 564 corresponds to one of a pair of terminals of the capacitor 600A, for example. The conductor 542a corresponds to the other of the pair of terminals of the capacitor 600A, for example.
The insulator 553 functions as a dielectric sandwiched between a pair of terminals of the capacitor 600A, for example.
The transistor 500A is provided above the conductor 542a and the insulator 595 of the capacitor 600A.
In the transistor 500A, the channel length direction is not substantially parallel to the substrate 311 but along the side surface of a later-described opening provided in the insulator 583.
The transistor 500A includes the conductor 542a functioning as one of the source electrode and the drain electrode, the conductor 542b functioning as the other of the source electrode and the drain electrode, a metal oxide 533, the insulator 555, and a conductor 565 functioning as a gate electrode, for example.
For the metal oxide 533, for example, the material that can be used for the oxide 530 included in the transistor 500 described in the above embodiment can be used.
In
The definition of the X direction, the Y direction, and the Z direction applies to the following drawings in some cases. The X direction, the Y direction, and the Z direction can be perpendicular to each other. In the description of a plan view in this specification and the like, the X direction may be referred to as the right side or the left side and the Y direction may be referred to as the upper side or the lower side. The right side may be rephrased as the X direction, the left side may be referred to as the −X direction, the upper side may be referred to as the Y direction, and the lower side may be referred to as the −Y direction in some cases.
The conductor 542a functions as one of the source electrode and the drain electrode of the transistor 500A. The conductor 542b functions as the other of the source electrode and the drain electrode of the transistor 500A. The insulator 555 functions as a gate insulating layer of the transistor 500A. The conductor 565 functions as the gate electrode of the transistor 500A.
In the metal oxide 533 between the source electrode and the drain electrode, the whole region overlapping with the gate electrode with the gate insulating layer therebetween functions as the channel formation region. The metal oxide 533 including a region functioning as the channel formation region is referred to as a semiconductor layer in some cases. In the metal oxide 533, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.
The insulator 596 is provided over the insulator 595 and the conductor 542a. The insulator 596 can function as an interlayer insulating layer. The interlayer insulating layer here can be a barrier insulating film that inhibits diffusion of impurities such as water and hydrogen (e.g., one or both of a hydrogen atom and a hydrogen molecule).
The insulator 583 (an insulator 583a and an insulator 583b) is provided over the insulator 596, and the conductor 542b is provided over the insulator 583. The insulator 583 can function as an interlayer insulating layer. The interlayer insulating layer here can be an interlayer film for separation of the source electrode and the gate electrode in 500A.
An oxide or an oxynitride is preferably used as the insulator 583a, for example. The insulator 583a is preferably formed using a film from which oxygen is released by heating. As the insulator 583a, silicon oxide or silicon oxynitride can be suitably used, for example. Oxygen release from the insulator 583a enables oxygen supply from the insulator 583a to the metal oxide 533. When oxygen is supplied from the insulator 583a to the metal oxide 533, in particular, the channel formation region of the metal oxide 533, oxygen vacancies (Vo), VoH, and hydrogen in the metal oxide 533 can be reduced. Consequently, the transistor 500A with favorable electrical characteristics and high reliability can be obtained.
The insulator 583b preferably includes a region containing more nitrogen than the insulator 583a, for example. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulator 583b. When silicon nitride or silicon nitride oxide is used for the insulator 583b, the insulator 583b can serve as a blocking layer that inhibits release of oxygen from the insulator 583a.
The insulator 596 and the insulator 583 each include an opening 601 reaching the conductor 542a. The conductor 542b includes an opening 603 reaching the opening 601. That is, the opening 603 includes a region overlapping with the opening 601.
As illustrated in
In the case where end portions are aligned or substantially aligned with each other, the end portions can also be said to match or substantially match. In the case where end portions match or substantially match and the case where planar shapes are the same or substantially the same, it can be said that outlines of stacked layers at least partly overlap with each other in a plan view. For example, the case of processing the upper layer and the lower layer with use of the same mask pattern or mask patterns that are partly the same is included. Note that, in some cases, the outlines do not completely overlap with each other and the upper layer is positioned inward from the lower layer or the upper layer is positioned outward from the lower layer; such cases are also represented by the expression “end portions substantially match” or the expression “planar shapes are substantially the same”.
The opening 601 can be formed using a resist mask used for the formation of the opening 603, for example. Specifically, first, the insulator 596 is formed over the conductor 542a and the insulator 595, the insulator 583 is formed over the insulator 596, a conductive film to be the conductor 542b is formed over the insulator 583, and a resist mask is formed over the conductive film. Then, the opening 603 is formed in the conductive film using the resist mask and then the opening 601 is formed in the insulator 596 and the insulator 583 using the resist mask, whereby the end portion of the opening 601 and the end portion of the opening 603 can be aligned or substantially aligned with each other. With such a structure, the process can be simplified.
The metal oxide 533 is provided to include a region positioned inside the opening 601 and the opening 603 to cover the opening 601 and the opening 603. The metal oxide 533 has a shape along the top surface and the side surface of the conductor 542b, the side surface of the insulator 583, the side surface of the insulator 596 and the top surface of the conductor 542a. The metal oxide 533 includes, for example, a region in contact with the top surface and the side surface of the conductor 542b, the side surface of the insulator 583, and the top surface of the conductor 542a.
The metal oxide 533 preferably covers the end portion of the conductor 542b on the opening 603 side. For example,
Although the metal oxide 533 has a single-layer structure in
The insulator 555 functioning as the gate insulating layer of the transistor 500A is provided to cover the opening 601 and the opening 603 and include a region positioned in the opening 601 and the opening 603. The insulator 555 is provided over the metal oxide 533, over the conductor 542b, and over the insulator 583. The insulator 555 can include a region in contact with the top surface and the side surface of the metal oxide 533, the top surface and the side surface of the conductor 542b, the top surface of the insulator 583, and the top surface of the insulator 596. The insulator 555 has a shape along the top surface of the insulator 596, the top surface of the insulator 583, the top surface and the side surface of the conductor 542b, and the top surface and the side surface of the metal oxide 533.
The conductor 565 functioning as the gate electrode of the transistor 500A can be provided over the insulator 555 and can include a region in contact with the top surface of the insulator 555. The conductor 565 includes a region overlapping with the metal oxide 533 with the insulator 555 therebetween. The conductor 565 has a shape along the shape of the top surface of the insulator 555.
For example, as illustrated in
The transistor 500A is what is called a top-gate transistor including a gate electrode above the metal oxide 533. Furthermore, since the bottom surface of the metal oxide 533 includes a region in contact with the source electrode and the drain electrode, the transistor 500A can be referred to as a TGBC (Top Gate Bottom Contact) transistor.
The transistor 500A can also be used as a transistor included in a circuit different from the memory cell MC, for example.
Here, the channel length and channel width of the transistor 500A are described with reference to
In the metal oxide 533, a region in contact with the conductor 542a functions as one of the source region and the drain region, a region in contact with the conductor 542b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as the channel formation region.
The channel length of the transistor 500A is a distance between the source region and the drain region. In
Here, the channel length L500 of the transistor 500A corresponds to the length of the side surface of the insulator 583 on the opening 601 side when seen from the XZ plane. In other words, the channel length L500 is determined depending on a thickness T583 of the insulator 583 and an angle θ583 formed by the side surface of the insulator 583 on the opening 601 side and the formation surface of the insulator 583 (here, the top surface of the conductor 542a), and is not affected by the performance of a light-exposure apparatus used for manufacturing the transistor. Thus, the channel length L500 can be a value smaller than that of the resolution limit of the light-exposure apparatus, which enables the transistor to have a minute size. For example, the channel length L500 is preferably larger than or equal to 0.010 μm and smaller than 3.0 μm, further preferably larger than or equal to 0.050 μm and smaller than 3.0 μm, still further preferably larger than or equal to 0.10 μm and smaller than 3.0 μm, yet still further preferably larger than or equal to 0.15 μm and smaller than 3.0 μm, yet still further preferably larger than or equal to 0.20 μm and smaller than 3.0 μm, yet still further preferably larger than or equal to 0.20 μm and smaller than 2.5 μm, yet still further preferably larger than or equal to 0.20 μm and smaller than 2.0 μm, yet still further preferably larger than or equal to 0.20 μm and smaller than 1.5 μm, yet still further preferably larger than or equal to 0.30 μm and smaller than 1.5 μm, yet still further preferably larger than or equal to 0.30 μm and smaller than or equal to 1.2 μm, yet still further preferably larger than or equal to 0.40 μm and smaller than or equal to 1.2 μm, yet still further preferably larger than or equal to 0.40 μm and smaller than or equal to 1.0 μm, yet still further preferably larger than or equal to 0.50 μm and smaller than or equal to 1.0 μm. In
When the transistor 500A is used as a transistor included in the memory cell MC, the memory cell MC can be miniaturized. Accordingly, a memory device with increased memory density can be obtained. Furthermore, when the channel length L500 is reduced, the on-state current of the transistor 500A can be increased, so that the memory cell MC can be driven at high speed.
The channel length L500 can be controlled by adjustment of the thickness T583 of the insulator 596 and the insulator 583 and the angle θ583.
The thickness T583 of the insulator 596 and the insulator 583 is preferably greater than or equal to 0.010 μm and less than 3.0 μm, further preferably greater than or equal to 0.050 μm and less than 3.0 μm, further preferably greater than or equal to 0.10 μm and less than 3.0 μm, still further preferably greater than or equal to 0.15 μm and less than 3.0 μm, yet still further preferably greater than or equal to 0.20 μm and less than 3.0 μm, yet still further preferably greater than or equal to 0.20 μm and less than 2.5 μm, yet still further preferably greater than or equal to 0.20 μm and less than 2.0 μm, yet still further preferably greater than or equal to 0.20 μm and less than 1.5 μm, yet still further preferably greater than or equal to 0.30 μm and less than 1.5 μm, yet still further preferably greater than or equal to 0.30 μm and less than or equal to 1.2 μm, yet still further preferably greater than or equal to 0.40 μm and less than or equal to 1.2 μm, yet still further preferably greater than or equal to 0.40 μm and less than or equal to 1.0 μm, yet still further preferably greater than or equal to 0.50 μm and less than or equal to 1.0 μm.
The side surfaces of the insulator 596 and the insulator 583 on the opening 601 side preferably each have a tapered shape. The angle θ583 formed by the side surfaces of the insulator 596 and the insulator 583 on the opening 601 side and the formation surface of the insulator 596 (here, the top surface of the conductor 542a) is preferably less than or equal to 90°. By reducing the angle θ583, the coverage with a layer provided over the insulator 583 (e.g., the metal oxide 533) can be improved. However, reducing the angle θ583 might reduce the contact area between the metal oxide 533 and the conductor 542a to increase the contact resistance between the metal oxide 533 and the conductor 542a. The angle θ583 is preferably greater than or equal to 45° and less than or equal to 90°, further preferably greater than or equal to 50° and less than or equal to 90°, further preferably greater than or equal to 55° and less than or equal to 90°, further preferably greater than or equal to 60° and less than or equal to 90°, further preferably greater than or equal to 60° and less than or equal to 85°, still further preferably greater than or equal to 65° and less than or equal to 85°, yet further preferably greater than or equal to 65° and less than or equal to 80°, yet still further preferably greater than or equal to 70° and less than or equal to 80°. When the angle θ583 is within the above range, the coverage with the layer formed over the conductor 542a and the insulator 583 (e.g., the metal oxide 533) can be improved, which can inhibit defects such as step disconnection or a void from being generated in the layer. In addition, the contact resistance between the metal oxide 533 and the conductor 542a can be reduced.
In this specification and the like, step disconnection refers to a phenomenon in which a layer, a film, or an electrode is split because of the shape of the formation surface (e.g., a step).
Although
The channel width of the transistor 500A is a width of the source region or a width of the drain region in the direction orthogonal to the channel length direction. In other words, the channel width is the width of the region where the metal oxide 533 is in contact with the conductor 542a or the width of the region where the metal oxide 533 is in contact with the conductor 542b in the direction orthogonal to the channel length direction. Here, the channel width of the transistor 500A is described as the width of the region where the metal oxide 533 and the conductor 542b are in contact with each other in the direction orthogonal to the channel length direction. In
The channel width W500 is determined by the planar shape of the opening 603. In
Since the size of the transistor 500A is small, by using the transistor 500A for the element layer 700, a semiconductor device with high memory density can be provided. Since the operation speed of the transistor 500A is high, by using the transistor 500A for a semiconductor device, a semiconductor device with high driving speed can be provided. Since the electrical characteristics of the transistor 500A are stable, by using the transistor 500A for a semiconductor device, a semiconductor device with high reliability can be provided. Since the amount of the off-state current of the transistor 500A is small, by using the transistor 500A for a semiconductor device, a semiconductor device with low power consumption can be provided.
This embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.
In this embodiment, a transistor whose channel formation region includes an oxide semiconductor (OS transistor) is described. In the description of the OS transistor, comparison with a transistor whose channel formation region includes silicon (also referred to as a Si transistor) is also briefly described.
An oxide semiconductor having a low carrier concentration is preferably used for the OS transistor. For example, the carrier concentration in a channel formation region of an oxide semiconductor is lower than or equal to 1×1018 cm−3, preferably lower than 1×1017 cm−3, further preferably lower than 1×1016 cm−3, still further preferably lower than 1×1013 cm−3, yet still further preferably lower than 1×1010 cm−3, and higher than or equal to 1×10−9 cm−3. In order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases. Charge trapped by the trap states in the oxide semiconductor takes a long time to disappear and might behave like fixed charge. Thus, a transistor whose channel formation region is formed in an oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.
Accordingly, in order to obtain stable electrical characteristics of the transistor, reducing the impurity concentration in the oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film be also reduced. Examples of the impurity include hydrogen and nitrogen. Note that an impurity in an oxide semiconductor refers to, for example, elements other than the main components of the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic % is regarded as an impurity.
When impurities and oxygen vacancies are in a channel formation region of an oxide semiconductor in an OS transistor, electrical characteristics of the OS transistor easily vary and the reliability thereof might worsen. In the OS transistor, a defect that is an oxygen vacancy in the oxide semiconductor into which hydrogen enters (hereinafter sometimes referred to as VoH) may be formed and may generate an electron serving as a carrier. When VoH is formed in the channel formation region, the donor concentration in the channel formation region increases in some cases. As the donor concentration in the channel formation region increases, the threshold voltage might vary. Therefore, when the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor is likely to have normally-on characteristics (characteristics with which, even when no voltage is applied to a gate electrode, a channel exists and current flows through the transistor). Accordingly, impurities, oxygen vacancies, and VoH are preferably reduced as much as possible in the channel formation region in the oxide semiconductor.
The band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), further preferably larger than or equal to 2 eV, still further preferably larger than or equal to 2.5 eV, yet still further preferably larger than or equal to 3.0 eV. With the use of an oxide semiconductor having a larger band gap than silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.
In a Si transistor, a short-channel effect (also referred to as SCE) appears as miniaturization of the transistor proceeds. Thus, it is difficult to miniaturize the Si transistor. One factor that causes the short-channel effect is a small band gap of silicon. By contrast, the OS transistor includes an oxide semiconductor that is a semiconductor material having a wide band gap, and thus can inhibit the short-channel effect. In other words, the OS transistor is a transistor where the short-channel effect does not appear or the short-channel effect hardly appears.
The short-channel effect refers to degradation of electrical characteristics which becomes obvious along with miniaturization of a transistor (a decrease in channel length). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value means the amount of change in gate voltage in the subthreshold region when the drain voltage keeps constant and the drain current changes by one order of magnitude.
The characteristic length is widely used as an indicator of resistance to a short-channel effect. The characteristic length is an indicator of curving of potential in a channel formation region. When the characteristic length is shorter, the potential rises more sharply, which means that the resistance to a short-channel effect is high.
The OS transistor is an accumulation-type transistor, and the Si transistor is an inversion-type transistor. Accordingly, an OS transistor has a shorter characteristic length between a source region and a channel formation region and a shorter characteristic length between a drain region and the channel formation region than a Si transistor. Therefore, an OS transistor has higher resistance to a short-channel effect than a Si transistor. That is, in the case where a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.
Even in the case where the carrier concentration in the oxide semiconductor is reduced until the channel formation region becomes an i-type or substantially i-type region, the conduction band minimum of the channel formation region in a short-channel transistor decreases because of the Conduction-Band-Lowering (CBL) effect; thus, a difference in energy of the conduction band minimum between the channel formation region and the source region or the drain region might decrease to higher than or equal to 0.1 eV and lower than or equal to 0.2 eV. Accordingly, the OS transistor can be regarded as having an n+/n−/n+accumulation-type junction-less transistor structure or an n+/n−/n+ accumulation-type non-junction transistor structure in which the channel formation region becomes an n−-type region and the source region and the drain region become n+-type regions.
The OS transistor with the above structure can have favorable electrical characteristics even when a semiconductor device is miniaturized or highly integrated. For example, the OS transistor can have favorable electrical characteristics even when the gate length of the OS transistor is less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 10 nm, less than or equal to 7 nm, or less than or equal to 6 nm and greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm. In contrast, it is sometimes difficult for the Si transistor to have a gate length less than or equal to 20 nm or less than or equal to 15 nm due to appearance of the short-channel effect. Thus, an OS transistor can be used as a transistor with a short channel length more suitably than a Si transistor. Note that the gate length refers to the length of a gate electrode in the direction in which carriers move inside a channel formation region during operation of a transistor, and corresponds to the width of a bottom surface of the gate electrode in a plan view of the transistor.
Miniaturization of an OS transistor can improve the high frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be greater than or equal to 50 GHz, preferably greater than or equal to 100 GHz, further preferably greater than or equal to 150 GHz at room temperature, for example.
As described above, the OS transistor has advantageous effects over the Si transistor, such as lower off-state current and the capability of being manufactured with a shorter channel length.
The configuration, structure, method, and the like described in this embodiment can be used in combination as appropriate with the configurations, structures, methods, and the like described in the other embodiments and the like.
This embodiment will describe an electronic component, an electronic device, a large computer, space equipment, and a data center (also referred to as a DC) that can use the semiconductor device described in the above embodiment. An electronic component, an electronic device, a large computer, space equipment, and a data center each using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, e.g., reducing power consumption.
The semiconductor device 710 includes a driver circuit layer 715 and an element layer 716. The element layer 716 has a structure in which a plurality of memory cell arrays are stacked. A stacked-layer structure of the driver circuit layer 715 and the element layer 716 can be a monolithic stacked-layer structure. In the monolithic stacked-layer structure, layers can be connected without using a through electrode technique such as a TSV (Through Silicon Via) and a bonding technique such as Cu—Cu direct bonding. The monolithic stacked-layer structure of the driver circuit layer 715 and the element layer 716 enables, for example, what is called an on-chip memory structure in which a memory is directly formed on a processor. The on-chip memory structure allows an interface portion between the processor and the memory to operate at high speed.
With the on-chip memory structure, the sizes of a connection wiring and the like can be smaller than those in the case where a through electrode technique such as a TSV is employed; thus, the number of connection pins can be increased. An increase in the number of connection pins enables parallel operations, which can increase the bandwidth of the memory (also referred to as a memory bandwidth).
It is preferable that the plurality of memory cell arrays included in the element layer 716 be formed using OS transistors and the plurality of memory cell arrays be monolithically stacked. The monolithic stacked-layer structure of a plurality of memory cell arrays can improve one or both of the bandwidth of the memory and the access latency of the memory. Note that a bandwidth refers to a data transfer volume per unit time, and access latency refers to time from access to start of data transmission. In the case where the element layer 716 is formed using Si transistors, it is difficult to obtain the monolithic stacked-layer structure as compared with the case where the element layer 716 is formed using OS transistors. Thus, an OS transistor is superior to a Si transistor in the monolithic stacked-layer structure.
The semiconductor device 710 may be referred to as a die. In this specification and the like, a die refers to each of chip pieces obtained by dividing a circuit pattern formed on a circular substrate (also referred to as a wafer) or the like into dice in the manufacturing process of a semiconductor chip, for example. Note that examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). A die obtained from a silicon substrate (also referred to as a silicon wafer) may be referred to as a silicon die, for example.
The electronic component 730 that includes the semiconductor device 710 as a high bandwidth memory (HBM) is illustrated as an example. The semiconductor device 735 can be used for an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).
As the package substrate 732, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used, for example. As the interposer 731, a silicon interposer or a resin interposer can be used, for example.
The interposer 731 includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 731 has a function of electrically connecting an integrated circuit provided on the interposer 731 to an electrode provided on the package substrate 732. Accordingly, the interposer is sometimes referred to as a “redistribution substrate” or an “intermediate substrate”. In some cases, a through electrode is provided in the interposer 731, and the through electrode is used to electrically connect an integrated circuit and the package substrate 732. Moreover, in the case of using a silicon interposer, a TSV can also be used as the through electrode.
An HBM needs to be connected to many wirings to achieve a wide memory bandwidth. Therefore, an interposer on which an HBM is mounted requires minute and densely formed wirings. For this reason, a silicon interposer is preferably used as the interposer on which an HBM is mounted.
In a SiP, an MCM, and the like each using a silicon interposer, a decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Furthermore, a surface of a silicon interposer has high planarity; thus, poor connection between the silicon interposer and an integrated circuit provided on the silicon interposer is less likely to occur. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer.
Meanwhile, in the case where a plurality of integrated circuits with different terminal pitches are electrically connected using a silicon interposer, a TSV, and the like, a space for the width of the terminal pitch and the like is needed. Thus, in the case where the size of the electronic component 730 is to be reduced, the width of the terminal pitches causes a problem, which sometimes makes it difficult to provide a large number of wirings for a wide memory bandwidth. For this reason, the above-described monolithic stacked-layer structure using OS transistors is suitable. A composite structure combining memory cell arrays stacked using a TSV and monolithically stacked memory cell arrays may be employed.
In addition, a heat sink (radiator plate) may be provided to overlap with the electronic component 730. In the case of providing a heat sink, the heights of integrated circuits provided on the interposer 731 are preferably equal to each other. For example, in the electronic component 730 described in this embodiment, the heights of the semiconductor device 710 and the semiconductor device 735 are preferably equal to each other.
To mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom portion of the package substrate 732.
The electronic component 730 can be mounted on another substrate by any of various mounting methods not limited to BGA and PGA. Examples of a mounting method include an SPGA (Staggered Pin Grid Array), an LGA (Land Grid Array), a QFP (Quad Flat Package), a QFJ (Quad Flat J-leaded package), and a QFN (Quad Flat Non-leaded package).
An electronic device 6600 illustrated in
Next, a perspective view of a large computer 5600 is illustrated in
The computer 5620 can have a structure in a perspective view illustrated in
The PC card 5621 illustrated in
The connection terminal 5629 has a shape with which the connection terminal 5629 can be inserted in the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.
The connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can serve as, for example, an interface for performing power supply, signal input, or the like to the PC card 5621. For another example, they can serve as an interface for outputting a signal calculated by the PC card 5621. Examples of the standard for each of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In the case where video signals are output from the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625, an example of the standard therefor is HDMI (registered trademark).
The semiconductor device 5626 includes a terminal (not illustrated) for inputting and outputting signals, and when the terminal is inserted in a socket (not illustrated) of the board 5622, the semiconductor device 5626 and the board 5622 can be electrically connected to each other.
The semiconductor device 5627 includes a plurality of terminals, and when the terminals are reflow-soldered, for example, to wirings of the board 5622, the semiconductor device 5627 and the board 5622 can be electrically connected to each other. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. As the semiconductor device 5627, the electronic component 730 can be used, for example.
The semiconductor device 5628 includes a plurality of terminals, and when the terminals are reflow-soldered, for example, to wirings of the board 5622, the semiconductor device 5628 and the board 5622 can be electrically connected to each other. An example of the semiconductor device 5628 is a memory device. As the semiconductor device 5628, the electronic component 709 can be used, for example.
The large computer 5600 can also function as a parallel computer. When the large computer 5600 is used as a parallel computer, large-scale computation necessary for artificial intelligence learning and inference can be performed, for example.
The semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as equipment that processes and stores information.
The semiconductor device of one embodiment of the present invention can include an OS transistor. A change in electrical characteristics of the OS transistor due to radiation irradiation is small. That is, the OS transistor is highly resistant to radiation and thus can be suitably used in an environment where radiation can enter. For example, the OS transistor can be suitably used in outer space.
Although not illustrated in
The amount of radiation in outer space is 100 or more times that on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) typified by X-rays and gamma rays and particle radiation typified by alpha rays, beta rays, neutron beams, proton beams, heavy-ion beams, and meson beams.
When the solar panel 6802 is irradiated with sunlight, electric power required for operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight or in a situation where the amount of sunlight with which the solar panel is irradiated is small, the amount of generated electric power is small. Accordingly, electric power required for operation of the artificial satellite 6800 might not be generated. In order to operate the artificial satellite 6800 even with a small amount of generated electric power, the artificial satellite 6800 is preferably provided with the secondary battery 6805. Note that a solar panel is referred to as a solar cell module in some cases.
The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and the signal can be received by a ground-based receiver or another artificial satellite, for example. When the signal transmitted by the artificial satellite 6800 is received, the position of a receiver that receives the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.
The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is formed using one or more selected from a CPU, a GPU, and a memory device, for example. Note that the semiconductor device of one embodiment of the present invention is suitably used for the control device 6807. A change in electrical characteristics due to radiation irradiation is smaller in an OS transistor than in a Si transistor. That is, the OS transistor has high reliability and thus can be suitably used even in an environment where radiation can enter.
The artificial satellite 6800 can include a sensor. For example, with a structure including a visible light sensor, the artificial satellite 6800 can have a function of sensing sunlight reflected by a ground-based object. Alternatively, with a structure including a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the surface of the earth. Thus, the artificial satellite 6800 can function as an earth observing satellite, for example.
Although the artificial satellite is described as an example of space equipment in this embodiment, one embodiment of the present invention is not limited thereto. The semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, or a space probe, for example.
As described above, the OS transistor has excellent effects of achieving wide memory bandwidth and being highly resistant to radiation as compared with the Si transistor.
The semiconductor device of one embodiment of the present invention can be suitably used for a storage system in a data center, for example. Long-term management of data, such as guarantee of data immutability, is required for the data center. The long-term management of data needs an increase in building size for, for example, setting a storage and a server for storing an enormous amount of data, ensuring stable power supply for data retention, and ensuring cooling equipment for data retention.
With the use of the semiconductor device of one embodiment of the present invention for the storage system used in the data center, electric power required for data retention can be reduced and a semiconductor device retaining data can be downsized. Thus, downsizing of the storage system, downsizing of the power supply for data retention, downscaling of the cooling equipment, and the like can be achieved. This can reduce the space of the data center.
Since the semiconductor device of one embodiment of the present invention has low power consumption, heat generation from a circuit can be reduced. Accordingly, it is possible to reduce adverse effects of the heat generation on the circuit itself, a peripheral circuit, and a module. Furthermore, the use of the semiconductor device of one embodiment of the present invention enables a data center that operates stably even in a high-temperature environment. Thus, the reliability of the data center can be increased.
The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The host 7001 may be connected to another host 7001 through a network.
The data access speed, i.e., the time taken for storing and outputting data, of the storage 7003 is shortened by using a flash memory, but is considerably longer than the data access speed of a DRAM that can be used as a cache memory in the storage. In the storage system, in order to solve the problem of low access speed of the storage 7003, a cache memory is normally provided in the storage to shorten the time for data storage and output.
The cache memories are used in the storage control circuit 7002 and the storage 7003. Data transmitted between the host 7001 and the storage 7003 are stored in the cache memories in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.
The use of an OS transistor as a transistor for storing data in the cache memory to retain a potential based on data can reduce the frequency of refreshing, so that power consumption can be reduced. Furthermore, downsizing is possible by stacking memory cell arrays.
Note that the use of the semiconductor device of one embodiment of the present invention for one or more selected from an electronic component, an electronic device, a large computer, space equipment, and a data center is expected to produce an effect of reducing power consumption. While the demand for energy is expected to increase with higher performance or higher integration of semiconductor devices, the emission amount of greenhouse effect gases typified by carbon dioxide (CO2) can be reduced with the use of the semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention can be effectively used as one of the global warming countermeasures because of its low power consumption.
The configuration, structure, method, and the like described in this embodiment can be used in combination as appropriate with the configurations, structures, methods, and the like described in the other embodiments and the like.
<Supplementary Notes on Description in this Specification and the Like>
The following are notes on the description of the above embodiments and the structures in the embodiments.
One embodiment of the present invention can be constituted by combining, as appropriate, the structure described in each embodiment with the structures described in the other embodiments. In the case where a plurality of structure examples are described in one embodiment, the structure examples can be combined as appropriate.
Note that content (or may be part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or may be part of the content) described in the embodiment and/or content (or may be part of the content) described in another embodiment or other embodiments.
Note that in each embodiment, content described in the embodiment is content described using a variety of diagrams or content described with text disclosed in the specification.
Note that by combining a diagram (or may be part thereof) described in one embodiment with another part of the diagram, a different diagram (or may be part thereof) described in the embodiment, and/or a diagram (or may be part thereof) described in another embodiment or other embodiments, much more diagrams can be formed.
In this specification and the like, components are classified on the basis of the functions, and shown as blocks independent of each other in block diagrams. However, in an actual circuit or the like, it is difficult to separate components on the basis of the functions, and there is such a case where one circuit is associated with a plurality of functions or a case where a plurality of circuits are associated with one function. Therefore, blocks in the block diagrams are not limited by the components described in this specification, and the description can be changed appropriately depending on the situation.
In the drawings, the size, the layer thickness, or the region is shown with given magnitude for description convenience. Therefore, they are not limited to the illustrated scale. Note that the drawings are schematically shown for clarity, and embodiments of the present invention are not limited to shapes, values or the like shown in the drawings. For example, variations in signal, voltage, or current due to noise, variations in signal, voltage, or current due to difference in timing, or the like can be included.
In this specification and the like, expressions “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used in the description of the connection relation of a transistor. This is because the source and the drain of the transistor change depending on the structure, operating conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (drain) terminal, a source (drain) electrode, or the like as appropriate depending on the situation.
In this specification and the like, the term “electrode” or “wiring” does not limit the function of the component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Furthermore, the term “electrode” or “wiring” also includes the case where a plurality of “electrodes” or “wirings” are formed in an integrated manner, for example.
In this specification and the like, “voltage” and “potential” can be interchanged with each other as appropriate. Voltage refers to a potential difference from a reference potential, and when the reference potential is a ground voltage, for example, voltage can be replaced with potential. The ground potential does not necessarily mean 0 V. Note that potentials are relative values, and a potential applied to a wiring or the like is sometimes changed depending on the reference potential.
Note that in this specification and the like, the terms such as “film” and “layer” can be interchanged with each other depending on the case or according to circumstances. For example, the term “conductive layer” can be replaced with the term “conductive film” in some cases. As another example, the term “insulating film” can be replaced with the term “insulating layer” in some cases.
In this specification and the like, a switch has a function of controlling whether current flows or not by being in a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch has a function of selecting and changing a current path.
In this specification and the like, channel length of a planar transistor refers to, for example, the distance between a source and a drain in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is in an on state) and a gate overlap with each other or a region where a channel is formed in a top view of the transistor.
In this specification and the like, channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap with each other or a region where a channel is formed.
In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit structure, a device structure, or the like. Furthermore, a terminal, a wiring, or the like can be referred to as a node.
In this specification and the like, the expression “A and B are connected” means the case where A and B are electrically connected. Here, the expression “A and B are electrically connected” means connection that enables electrical signal transmission between A and B in the case where an object (which refers to an element such as a switch, a transistor element, or a diode, a circuit including the element and a wiring, or the like) exists between A and B. Note that the case where A and B are electrically connected includes the case where A and B are directly connected. Here, the expression “A and B are directly connected” means connection that enables electrical signal transmission between A and B through a wiring (or an electrode) or the like, not through the above object. In other words, direct connection refers to connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.
10: memory device, 20: element layer, 21: precharge circuit, 22: sense amplifier, 23: reading circuit, 30: element layer, 31: cell array, 32: memory cell, 33: transistor, 34: capacitor, 40: control circuit, 50: input/output circuit
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-123244 | Aug 2022 | JP | national |
| 2022-151115 | Sep 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2023/057377 | 7/20/2023 | WO |
