Arrangements for setting the Unit Under Test [UUT] in a test mode

Industry

CPC
G01R31/31701

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31701Arrangements for setting the Unit Under Test [UUT] in a test mode

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method for checking DFT circuit, test platform, storage medium and...
- Patent number 12,174,250
- Issue date Dec 24, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Teng Shi
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for fault detection and reporting through seria...
- Patent number 12,169,218
- Issue date Dec 17, 2024
- Maxim Integrated Products, Inc.
- Ling Liu
- G01 - MEASURING TESTING
Information Patent Grant
System capable of detecting failure of component of system and meth...
- Patent number 11,988,709
- Issue date May 21, 2024
- DEEPX CO., LTD.
- Lok Won Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuit using clock gating scheme to hold capture procedure an...
- Patent number 11,959,965
- Issue date Apr 16, 2024
- Samsung Electronics Co., Ltd.
- Giha Nam
- G01 - MEASURING TESTING
Information Patent Grant
Single pin DFT architecture for USBPD ICs
- Patent number 11,933,841
- Issue date Mar 19, 2024
- SILICONCH SYSTEMS PVT LTD
- Munnangi Sirisha
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solid state ESD SiC simulator
- Patent number 11,846,664
- Issue date Dec 19, 2023
- FEI Company
- Marcos Hernandez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
United states test controller for system-on-chip validation
- Patent number 11,841,396
- Issue date Dec 12, 2023
- MARVELL ASIA PTE. LTD.
- Sameer Vaidya
- G01 - MEASURING TESTING
Information Patent Grant
Electrical circuit for testing primary internal signals of an ASIC
- Patent number 11,808,809
- Issue date Nov 7, 2023
- Robert Bosch GmbH
- Carsten Hermann
- G01 - MEASURING TESTING
Information Patent Grant
Smart storage of shutdown LBIST status
- Patent number 11,796,591
- Issue date Oct 24, 2023
- Ambarella International LP
- Praveen Jaini
- G01 - MEASURING TESTING
Information Patent Grant
Scan test device and scan test method
- Patent number 11,789,073
- Issue date Oct 17, 2023
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for identifying flaws and bugs in integrated ci...
- Patent number 11,733,295
- Issue date Aug 22, 2023
- International Business Machines Corporation
- Arun Joseph
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing artificial intelligence chip, devi...
- Patent number 11,714,128
- Issue date Aug 1, 2023
- KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
- Ziyu Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional tester for printed circuit boards, and associated system...
- Patent number 11,686,759
- Issue date Jun 27, 2023
- CheckSum, LLC
- Jonathan Allen Feucht
- G01 - MEASURING TESTING
Information Patent Grant
System and method of testing single DUT through multiple cores in p...
- Patent number 11,686,768
- Issue date Jun 27, 2023
- Test Research, Inc.
- Ching-Chih Lin
- G01 - MEASURING TESTING
Information Patent Grant
Implementing a JTAG device chain in multi-die integrated circuit
- Patent number 11,675,006
- Issue date Jun 13, 2023
- Xilinx, Inc.
- Roger D. Flateau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory temperature controlling method and memory temperature contro...
- Patent number 11,635,460
- Issue date Apr 25, 2023
- Hefei Core Storage Electronic Limited
- Biao Zhang
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with self-test circuit, method for operating an...
- Patent number 11,619,668
- Issue date Apr 4, 2023
- Infineon Technologies AG
- Daniel Tille
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock control system for scan chains
- Patent number 11,604,223
- Issue date Mar 14, 2023
- NXP USA, INC.
- Himanshu Mangal
- G01 - MEASURING TESTING
Information Patent Grant
Measurement of internal wire delay
- Patent number 11,567,128
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Toshiyuki Sato
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface circuit
- Patent number 11,519,959
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for facilitating built-in self-test of system-on-...
- Patent number 11,513,153
- Issue date Nov 29, 2022
- NXP USA, INC.
- Rohan Poudel
- G01 - MEASURING TESTING
Information Patent Grant
Extended JTAG controller and method for functional reset using the...
- Patent number 11,493,553
- Issue date Nov 8, 2022
- COMMSOLID GMBH
- Uwe Porst
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for debugging integrated circuit systems using...
- Patent number 11,442,106
- Issue date Sep 13, 2022
- Western Digital Technologies, Inc.
- Amir Segev
- G01 - MEASURING TESTING
Information Patent Grant
Self-calibrating deskew fixture
- Patent number 11,428,732
- Issue date Aug 30, 2022
- Keysight Technologies, Inc.
- Edward Vernon Brush
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for fault detection and reporting through seria...
- Patent number 11,422,182
- Issue date Aug 23, 2022
- Maxim Integrated Products, Inc.
- Ling Liu
- G01 - MEASURING TESTING
Information Patent Grant
Methods and systems for single-event upset fault injection testing
- Patent number 11,378,622
- Issue date Jul 5, 2022
- Raytheon Company
- Patrick Fleming
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital circuit robustness verification method and system
- Patent number 11,353,509
- Issue date Jun 7, 2022
- Realtek Semiconductor Corporation
- Wen-Yi Mao
- G01 - MEASURING TESTING
Information Patent Grant
System and method for parallel testing of electronic device
- Patent number 11,340,292
- Issue date May 24, 2022
- STMicroelectronics International N.V.
- Rajesh Narwal
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT
- Publication number 20240313781
- Publication date Sep 19, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G01 - MEASURING TESTING
Information Patent Application
NPU CAPABLE OF BEING TESTED DURING RUNTIME
- Publication number 20240264226
- Publication date Aug 8, 2024
- DEEPX CO., LTD.
- Lok Won KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST MODE CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM, AND...
- Publication number 20240159828
- Publication date May 16, 2024
- SK HYNIX INC.
- Jin Suk OH
- G01 - MEASURING TESTING
Information Patent Application
SOLID STATE ESD SIC SIMULATOR
- Publication number 20240044964
- Publication date Feb 8, 2024
- FEI Company
- Marcos Hernandez
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR CHECKING DFT CIRCUIT, TEST PLATFORM, STORAGE MEDIUM AND...
- Publication number 20230358805
- Publication date Nov 9, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Teng SHI
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AN...
- Publication number 20230152372
- Publication date May 18, 2023
- Samsung Electronics Co., Ltd.
- GIHA NAM
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND SYSTEMS FOR IDENTIFYING FLAWS AND BUGS IN INTEGRATED CI...
- Publication number 20230080463
- Publication date Mar 16, 2023
- International Business Machines Corporation
- Arun Joseph
- G01 - MEASURING TESTING
Information Patent Application
MEMORY TEMPERATURE CONTROLLING METHOD AND MEMORY TEMPERATURE CONTRO...
- Publication number 20230074401
- Publication date Mar 9, 2023
- Hefei Core Storage Electronic Limited
- Biao Zhang
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20230058458
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND DEVICES FOR INTELLIGENT INTEGRATED TESTING
- Publication number 20220390512
- Publication date Dec 8, 2022
- TestEye Technologies Inc.
- Edward Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR FAULT DETECTION AND REPORTING THROUGH SERIA...
- Publication number 20220390507
- Publication date Dec 8, 2022
- Maxim Integrated Products, Inc.
- Ling LIU
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...
- Publication number 20220334181
- Publication date Oct 20, 2022
- NXP USA, Inc.
- Rohan Poudel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR PARALLEL TESTING OF ELECTRONIC DEVICE
- Publication number 20220276302
- Publication date Sep 1, 2022
- STMicroelectronics International N.V.
- Rajesh Narwal
- G01 - MEASURING TESTING
Information Patent Application
SINGLE PIN DFT ARCHITECTURE FOR USBPD ICs
- Publication number 20220244309
- Publication date Aug 4, 2022
- SILICONCH SYSTEMS PVT LTD
- Munnangi SIRISHA
- G01 - MEASURING TESTING
Information Patent Application
FUNCTIONAL TESTER FOR PRINTED CIRCUIT BOARDS, AND ASSOCIATED SYSTEM...
- Publication number 20220236315
- Publication date Jul 28, 2022
- CheckSum, LLC
- Jonathan Allen Feucht
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM CAPABLE OF DETECTING FAILURE OF COMPONENT OF SYSTEM AND METH...
- Publication number 20220206068
- Publication date Jun 30, 2022
- DEEPX CO., LTD.
- Lok Won KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DEBUGGING INTEGRATED CIRCUIT SYSTEMS USING...
- Publication number 20220187369
- Publication date Jun 16, 2022
- Western Digital Technologies, Inc.
- Amir Segev
- G01 - MEASURING TESTING
Information Patent Application
IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20220170983
- Publication date Jun 2, 2022
- Xilinx, Inc.
- Roger D. FLATEAU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASUREMENT OF INTERNAL WIRE DELAY
- Publication number 20210356520
- Publication date Nov 18, 2021
- Micron Technology, Inc.
- Toshiyuki Sato
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210325456
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED JTAG CONTROLLER AND METHOD FOR FUNCTIONAL RESET USING THE...
- Publication number 20210325461
- Publication date Oct 21, 2021
- COMMSOLID GMBH
- Uwe PORST
- G01 - MEASURING TESTING
Information Patent Application
IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20210311115
- Publication date Oct 7, 2021
- Xilinx, Inc.
- Roger D. FLATEAU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR FAULT DETECTION AND REPORTING THROUGH SERIA...
- Publication number 20210302488
- Publication date Sep 30, 2021
- Maxim Integrated Products, Inc.
- Ling LIU
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER ACCESSIBLE TEST ACCESS PORT CONTROLS
- Publication number 20210270894
- Publication date Sep 2, 2021
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Application
SECURE SCAN ENTRY
- Publication number 20210263098
- Publication date Aug 26, 2021
- Silicon Laboratories Inc.
- Mudit Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-TEST OF AN ASYNCHRONOUS CIRCUIT
- Publication number 20210190862
- Publication date Jun 24, 2021
- CRYPTOGRAPHY RESEARCH, INC.
- Matthew Pond Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self Test for Safety Logic
- Publication number 20210148976
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Sundarrajan Rangachari
- G01 - MEASURING TESTING
Information Patent Application
A DEBUGGING SOLUTION FOR MULTI-CORE PROCESSORS
- Publication number 20210123973
- Publication date Apr 29, 2021
- C-SKY Microsystems Co., Ltd.
- Taotao ZHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL CIRCUIT ROBUSTNESS VERIFICATION METHOD AND SYSTEM
- Publication number 20210072314
- Publication date Mar 11, 2021
- REALTEK SEMICONDUCTOR CORPORATION
- Wen-Yi MAO
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210072310
- Publication date Mar 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING

Arrangements for setting the Unit Under Test [UUT] in a test mode

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method for checking DFT circuit, test platform, storage medium and...

Systems and methods for fault detection and reporting through seria...

System capable of detecting failure of component of system and meth...

Test circuit using clock gating scheme to hold capture procedure an...

Single pin DFT architecture for USBPD ICs

Reduced signaling interface method and apparatus

Solid state ESD SiC simulator

United states test controller for system-on-chip validation

Electrical circuit for testing primary internal signals of an ASIC

Smart storage of shutdown LBIST status

Scan test device and scan test method

Integrated circuit with reduced signaling interface

Methods and systems for identifying flaws and bugs in integrated ci...

Method and apparatus for testing artificial intelligence chip, devi...

Functional tester for printed circuit boards, and associated system...

System and method of testing single DUT through multiple cores in p...

Implementing a JTAG device chain in multi-die integrated circuit

Memory temperature controlling method and memory temperature contro...

Integrated circuit with self-test circuit, method for operating an...

Clock control system for scan chains

Measurement of internal wire delay

Reduced signaling interface circuit

System and method for facilitating built-in self-test of system-on-...

Extended JTAG controller and method for functional reset using the...

Method and apparatus for debugging integrated circuit systems using...

Self-calibrating deskew fixture

Systems and methods for fault detection and reporting through seria...

Methods and systems for single-event upset fault injection testing

Digital circuit robustness verification method and system

System and method for parallel testing of electronic device

Patents Applicationslast 30 patents

PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT

NPU CAPABLE OF BEING TESTED DURING RUNTIME

TEST MODE CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM, AND...

SOLID STATE ESD SIC SIMULATOR

METHOD FOR CHECKING DFT CIRCUIT, TEST PLATFORM, STORAGE MEDIUM AND...

TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AN...

METHODS AND SYSTEMS FOR IDENTIFYING FLAWS AND BUGS IN INTEGRATED CI...

MEMORY TEMPERATURE CONTROLLING METHOD AND MEMORY TEMPERATURE CONTRO...

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

SYSTEMS AND DEVICES FOR INTELLIGENT INTEGRATED TESTING

SYSTEMS AND METHODS FOR FAULT DETECTION AND REPORTING THROUGH SERIA...

SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...

SYSTEM AND METHOD FOR PARALLEL TESTING OF ELECTRONIC DEVICE

SINGLE PIN DFT ARCHITECTURE FOR USBPD ICs

FUNCTIONAL TESTER FOR PRINTED CIRCUIT BOARDS, AND ASSOCIATED SYSTEM...

SYSTEM CAPABLE OF DETECTING FAILURE OF COMPONENT OF SYSTEM AND METH...

METHOD AND APPARATUS FOR DEBUGGING INTEGRATED CIRCUIT SYSTEMS USING...

IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT

MEASUREMENT OF INTERNAL WIRE DELAY

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

EXTENDED JTAG CONTROLLER AND METHOD FOR FUNCTIONAL RESET USING THE...

IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT

SYSTEMS AND METHODS FOR FAULT DETECTION AND REPORTING THROUGH SERIA...

CONTROLLER ACCESSIBLE TEST ACCESS PORT CONTROLS

SECURE SCAN ENTRY

SELF-TEST OF AN ASYNCHRONOUS CIRCUIT

Self Test for Safety Logic

A DEBUGGING SOLUTION FOR MULTI-CORE PROCESSORS

DIGITAL CIRCUIT ROBUSTNESS VERIFICATION METHOD AND SYSTEM

REDUCED SIGNALING INTERFACE METHOD & APPARATUS