Board Level Test

Industry

CPC
G01R31/318508

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318508Board Level Test

Industries

Patents Grantslast 30 patents

Information Patent Grant
Test system, test method, and non-transitory computer readable medium
- Patent number 12,146,910
- Issue date Nov 19, 2024
- Kioxia Corporation
- Kazuhiko Nakahara
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus to implement a boundary scan for shared analo...
- Patent number 12,130,329
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 12,007,441
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 11,675,007
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Core partition circuit and testing device
- Patent number 11,624,782
- Issue date Apr 11, 2023
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Yunhao Xing
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test coverage rate improvement system for pins of tested circuit bo...
- Patent number 11,435,400
- Issue date Sep 6, 2022
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Qiu-Yue Duan
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 11,428,736
- Issue date Aug 30, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method of and an arrangement for analyzing manufacturing defects of...
- Patent number 11,293,979
- Issue date Apr 5, 2022
- Peter Shun Shen Wang
- G01 - MEASURING TESTING
Information Patent Grant
IC first/second surfaces contact points, test control port, paralle...
- Patent number 11,047,912
- Issue date Jun 29, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Boundary scan and wrapper circuitry with state machine and multiple...
- Patent number 10,928,445
- Issue date Feb 23, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Sleek serial interface for a wrapper boundary register (device and...
- Patent number 10,591,537
- Issue date Mar 17, 2020
- X-FAB SEMICONDUCTOR FOUNDRIES GMBH
- Ulrike Mueller-Schniek
- G01 - MEASURING TESTING
Information Patent Grant
Tap Dual Port Router, First, Second Multiplexer, First, Second Gating
- Patent number 10,564,220
- Issue date Feb 18, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Wrapper serial port externally accessible pin providing additional...
- Patent number 10,401,426
- Issue date Sep 3, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test mode isolation and power reduction in embedded core-based digi...
- Patent number 10,310,013
- Issue date Jun 4, 2019
- Samsung Electronics Co., Ltd.
- Guangyuan Kelvin Ge
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device and scan test method including writing and rea...
- Patent number 10,295,597
- Issue date May 21, 2019
- Renesas Electronics Corporation
- Yoichi Maeda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tap dual port router with update lead and gated updatedr
- Patent number 10,197,626
- Issue date Feb 5, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TAP and gating enable, CaptureDR, capture, and gated CaptureDR signals
- Patent number 10,162,001
- Issue date Dec 25, 2018
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sleek serial interface for a wrapper boundary register (device and...
- Patent number 10,151,794
- Issue date Dec 11, 2018
- X-Fab Semiconductor Foundries AG.
- Ulrike Mueller-Schniek
- G01 - MEASURING TESTING
Information Patent Grant
Gating tap register control bus and auxiliary/wrapper test bus
- Patent number 9,810,737
- Issue date Nov 7, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for testing through silicon vias in 3D integrated circuits
- Patent number 9,784,790
- Issue date Oct 10, 2017
- International Business Machines Corporation
- Raphael P. Robertazzi
- G01 - MEASURING TESTING
Information Patent Grant
Tap dual port router circuitry with gated shiftDR and clockDR
- Patent number 9,753,085
- Issue date Sep 5, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Core wrappers, I/O circuitry, link instruction register with and gate
- Patent number 9,618,581
- Issue date Apr 11, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing through silicon vias in 3D integrated circuits
- Patent number 9,588,174
- Issue date Mar 7, 2017
- International Business Machines Corporation
- Raphael Peter Robertazzi
- G01 - MEASURING TESTING
Information Patent Grant
Scan wrapper circuit for integrated circuit
- Patent number 9,568,551
- Issue date Feb 14, 2017
- FREESCALE SEMICONDUCTOR, INC.
- Sagar Kataria
- G01 - MEASURING TESTING
Information Patent Grant
TAP gated updateDR output AUX test control of WSP update
- Patent number 9,535,124
- Issue date Jan 3, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tap dual port router circuitry with update and capture inputs
- Patent number 9,513,336
- Issue date Dec 6, 2016
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing embedded systems
- Patent number 9,494,651
- Issue date Nov 15, 2016
- Honeywell Limited
- Andrzej Wlodzimierz Nawrocki
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Semiconductor device including memory circuit and logic array
- Patent number 9,494,644
- Issue date Nov 15, 2016
- Semiconductor Energy Laboratory Co., Ltd.
- Yoshiyuki Kurokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core wrapper link instruction register controls responsive to selec...
- Patent number 9,377,509
- Issue date Jun 28, 2016
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TAP with AUX capture input, gated capture and shiftDR outputs
- Patent number 9,329,233
- Issue date May 3, 2016
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Apparatus and Method for Testing Semiconductor Devices
- Publication number 20240329134
- Publication date Oct 3, 2024
- Testmetrix, Inc.
- Christian O. Cojocneanu
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALO...
- Publication number 20240288496
- Publication date Aug 29, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
TEST SYSTEM, TEST METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
- Publication number 20230400514
- Publication date Dec 14, 2023
- KIOXIA Corporation
- Kazuhiko NAKAHARA
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20220381821
- Publication date Dec 1, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND DEVICE FOR TESTING INTEGRATED CIRCUIT
- Publication number 20220299567
- Publication date Sep 22, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Zhi Qu
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and Method for Testing Semiconductor Devices
- Publication number 20220137132
- Publication date May 5, 2022
- Testmetrix, Inc.
- Christian O. Cojocneanu
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20210270895
- Publication date Sep 2, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20200166572
- Publication date May 28, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS
- Publication number 20190346505
- Publication date Nov 14, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLEEK SERIAL INTERFACE FOR A WRAPPER BOUNDARY REGISTER (DEVICE AND...
- Publication number 20190170821
- Publication date Jun 6, 2019
- X-FAB SEMICONDUCTOR FOUNDRIES GmbH
- Ulrike Mueller-Schniek
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20190120900
- Publication date Apr 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS
- Publication number 20190064267
- Publication date Feb 28, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPONENT COMMUNICATIONS IN SYSTEM-IN-PACKAGE SYSTEMS
- Publication number 20180321313
- Publication date Nov 8, 2018
- Octavo Systems LLC
- Kevin Michael Troy
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SEMICONDUCTOR DEVICE AND SCAN TEST METHOD
- Publication number 20180059183
- Publication date Mar 1, 2018
- RENESAS ELECTRONICS CORPORATION
- Yoichi MAEDA
- G01 - MEASURING TESTING
Information Patent Application
GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS
- Publication number 20180031633
- Publication date Feb 1, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIET TEST ARCHITECTURE
- Publication number 20170315171
- Publication date Nov 2, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST APPARATUS AND OPERATING METHOD THEREOF
- Publication number 20140380110
- Publication date Dec 25, 2014
- SK HYNIX INC.
- Ki-Ho KIM
- G01 - MEASURING TESTING
Information Patent Application
INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS
- Publication number 20140237309
- Publication date Aug 21, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS
- Publication number 20140082442
- Publication date Mar 20, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Equipment test method and associated test tool and test system
- Publication number 20140041465
- Publication date Feb 13, 2014
- Bertrand Crouzet
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S...
- Publication number 20130346816
- Publication date Dec 26, 2013
- Sankaran M. Menon
- G01 - MEASURING TESTING
Information Patent Application
Interconnections for Plural and Hierarchical P1500 Test Wrappers
- Publication number 20130275826
- Publication date Oct 17, 2013
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Interconnections for Plural and Hierarchical P1500 Test Wrappers
- Publication number 20130268816
- Publication date Oct 10, 2013
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Interconnections for Plural and Hierarchical P1500 Test Wrappers
- Publication number 20130254610
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS
- Publication number 20130227513
- Publication date Aug 29, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS
- Publication number 20130185608
- Publication date Jul 18, 2013
- QUALCOMM Incorporated
- Sudipta Bhawmik
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20130047047
- Publication date Feb 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS
- Publication number 20130024737
- Publication date Jan 24, 2013
- Stichting IMEC Nederland
- Erik Jan Marinissen
- G01 - MEASURING TESTING
Information Patent Application
INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS
- Publication number 20120317452
- Publication date Dec 13, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Board Level Test

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test system, test method, and non-transitory computer readable medium

Methods and apparatus to implement a boundary scan for shared analo...

3D stacked die test architecture

3D stacked die test architecture

Core partition circuit and testing device

Test coverage rate improvement system for pins of tested circuit bo...

3D stacked die test architecture

Method of and an arrangement for analyzing manufacturing defects of...

IC first/second surfaces contact points, test control port, paralle...

Boundary scan and wrapper circuitry with state machine and multiple...

Sleek serial interface for a wrapper boundary register (device and...

Tap Dual Port Router, First, Second Multiplexer, First, Second Gating

Wrapper serial port externally accessible pin providing additional...

Test mode isolation and power reduction in embedded core-based digi...

Semiconductor device and scan test method including writing and rea...

Tap dual port router with update lead and gated updatedr

TAP and gating enable, CaptureDR, capture, and gated CaptureDR signals

Sleek serial interface for a wrapper boundary register (device and...

Gating tap register control bus and auxiliary/wrapper test bus

Method for testing through silicon vias in 3D integrated circuits

Tap dual port router circuitry with gated shiftDR and clockDR

Core wrappers, I/O circuitry, link instruction register with and gate

Method for testing through silicon vias in 3D integrated circuits

Scan wrapper circuit for integrated circuit

TAP gated updateDR output AUX test control of WSP update

Tap dual port router circuitry with update and capture inputs

Method for testing embedded systems

Semiconductor device including memory circuit and logic array

Core wrapper link instruction register controls responsive to selec...

TAP with AUX capture input, gated capture and shiftDR outputs

Patents Applicationslast 30 patents

Apparatus and Method for Testing Semiconductor Devices

3D STACKED DIE TEST ARCHITECTURE

METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALO...

TEST SYSTEM, TEST METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

3D STACKED DIE TEST ARCHITECTURE

METHOD AND DEVICE FOR TESTING INTEGRATED CIRCUIT

Apparatus and Method for Testing Semiconductor Devices

3D STACKED DIE TEST ARCHITECTURE

3D STACKED DIE TEST ARCHITECTURE

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

SLEEK SERIAL INTERFACE FOR A WRAPPER BOUNDARY REGISTER (DEVICE AND...

3D STACKED DIE TEST ARCHITECTURE

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

COMPONENT COMMUNICATIONS IN SYSTEM-IN-PACKAGE SYSTEMS

SEMICONDUCTOR DEVICE AND SCAN TEST METHOD

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

3D STACKED DIET TEST ARCHITECTURE

TEST APPARATUS AND OPERATING METHOD THEREOF

INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

Equipment test method and associated test tool and test system

METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S...

Interconnections for Plural and Hierarchical P1500 Test Wrappers

Interconnections for Plural and Hierarchical P1500 Test Wrappers

Interconnections for Plural and Hierarchical P1500 Test Wrappers

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS

3D STACKED DIE TEST ARCHITECTURE

TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS

INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS