Built-in arrangements for testing

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GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/12Built-in arrangements for testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Memory device including sense amplifying circuit
- Patent number 12,315,579
- Issue date May 27, 2025
- SK Hynix Inc.
- Yeonsu Jang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and operating method of the memory device
- Patent number 12,315,582
- Issue date May 27, 2025
- SK hynix Inc.
- Min Ho Her
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable MBIST method based on adaptive march algorithm
- Patent number 12,308,085
- Issue date May 20, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing memory device
- Patent number 12,308,086
- Issue date May 20, 2025
- NANYA TECHNOLOGY CORPORATION
- Jui-Chung Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
In-situ detection of anomalies in integrated circuits using machine...
- Patent number 12,307,747
- Issue date May 20, 2025
- Intel Corporation
- Sriram R. Vangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Volatile memory devices and methods of operating same to improve re...
- Patent number 12,308,083
- Issue date May 20, 2025
- Samsung Electronics Co., Ltd.
- Junyoung Ko
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable testing and repair system for non-volatile memory
- Patent number 12,308,081
- Issue date May 20, 2025
- iSTART-TEK INC.
- Cheng-Yen Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Interactive DRAM signal analyzer and method of analyzing and calibr...
- Patent number 12,308,084
- Issue date May 20, 2025
- COSIGNON
- Sung Ho Park
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor memory devices that support enhanced data recovery op...
- Patent number 12,308,082
- Issue date May 20, 2025
- Samsung Electronics Co., Ltd.
- Seungjun Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable scan chain architecture for multi-port memory
- Patent number 12,300,338
- Issue date May 13, 2025
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including a sub-controller and operating method of th...
- Patent number 12,300,341
- Issue date May 13, 2025
- SK Hynix Inc.
- Jong Joo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing a non-volatile memory
- Patent number 12,300,342
- Issue date May 13, 2025
- Infineon Technologies LLC
- Bogdan Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting memory power consumption
- Patent number 12,300,340
- Issue date May 13, 2025
- Microsoft Technology Licensing, LLC
- Ori Laslo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory device test method, and test system
- Patent number 12,300,344
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Hong-Jun Jin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory interface and semiconductor memory device and semiconductor...
- Patent number 12,293,801
- Issue date May 6, 2025
- Samsung Electronics Co., Ltd.
- Hojun Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with layout adaptive problematic word line dete...
- Patent number 12,293,800
- Issue date May 6, 2025
- SanDisk Technologies, Inc.
- Xuan Tian
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test burst patterns based on architecture of memory
- Patent number 12,293,803
- Issue date May 6, 2025
- Micron Technology, Inc.
- William Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit and receiving circuit having test function
- Patent number 12,288,589
- Issue date Apr 29, 2025
- SK hynix Inc.
- Gi Moon Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit for detecting word line defect and semiconductor appar...
- Patent number 12,283,331
- Issue date Apr 22, 2025
- SK hynix Inc.
- Suk Hwan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit retiring to mitigate bit errors
- Patent number 12,283,333
- Issue date Apr 22, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Component die validation built-in self-test (VBIST) engine
- Patent number 12,282,064
- Issue date Apr 22, 2025
- Ampere Computing LLC
- Sandeep Brahmadathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system
- Patent number 12,283,330
- Issue date Apr 22, 2025
- Kioxia Corporation
- Tsukasa Tokutomi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory BIST circuit and method
- Patent number 12,283,332
- Issue date Apr 22, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device interface and method
- Patent number 12,277,056
- Issue date Apr 15, 2025
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method for operating the same including setting a...
- Patent number 12,277,967
- Issue date Apr 15, 2025
- Micron Technology, Inc.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing memory device
- Patent number 12,272,415
- Issue date Apr 8, 2025
- NANYA TECHNOLOGY CORPORATION
- Yaochang Chiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Vera detection method to catch erase fail
- Patent number 12,272,417
- Issue date Apr 8, 2025
- SanDisk Technologies, Inc.
- Parth Amin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device configured to reduce degradation of adjacent word lin...
- Patent number 12,272,403
- Issue date Apr 8, 2025
- Samsung Electronics Co., Ltd.
- Myoung-Ho Son
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for improving ECC operation of memories
- Patent number 12,266,410
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test circuit for row hammering in memory
- Patent number 12,266,413
- Issue date Apr 1, 2025
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY REPAIR CIRCUIT, A MEMORY REPAIR METHOD, AND A MEMORY DEVICE
- Publication number 20250166720
- Publication date May 22, 2025
- Samsung Electronics Co., Ltd.
- Hyunseok KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LASER DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
- Publication number 20250167139
- Publication date May 22, 2025
- Samsung Electronics Co., Ltd.
- Cheolhwan LIM
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVATION FUNCTIONS FOR ARTIFICIAL INTELLIGENCE OPERATIONS
- Publication number 20250157509
- Publication date May 15, 2025
- Micron Technology, Inc.
- Alberto Troia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERACTIVE DRAM SIGNAL ANALYZER AND METHOD OF ANALYZING AND CALIBR...
- Publication number 20250157558
- Publication date May 15, 2025
- COSIGNON
- Sung Ho PARK
- G01 - MEASURING TESTING
Information Patent Application
STORAGE DEVICE AND OPERATING METHOD THEREOF
- Publication number 20250157559
- Publication date May 15, 2025
- SK HYNIX INC.
- Jung Sik Choi
- G11 - INFORMATION STORAGE
Information Patent Application
TEST MODE STATE MACHINE FOR A MEMORY DEVICE
- Publication number 20250138744
- Publication date May 1, 2025
- Micron Technology, Inc.
- Rucha Deepak Geedh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND SEMICONDUCTO...
- Publication number 20250140332
- Publication date May 1, 2025
- Samsung Electronics Co., Ltd.
- Changyoung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION
- Publication number 20250140333
- Publication date May 1, 2025
- SK HYNIX INC.
- Dong Yoon KA
- G11 - INFORMATION STORAGE
Information Patent Application
SCHEME TO FETCH OPTIMAL READ PARAMETERS BY SKIPPING INVALID WORDLINES
- Publication number 20250140331
- Publication date May 1, 2025
- Western Digital Technologies, Inc.
- DARSHAN PAGARIYA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR ISOLATING FAULTY NAND TEMPERATURE SENSOR
- Publication number 20250140330
- Publication date May 1, 2025
- Western Digital Technologies, Inc.
- VARUN SHARMA
- G01 - MEASURING TESTING
Information Patent Application
STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS
- Publication number 20250130908
- Publication date Apr 24, 2025
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY TESTING SYSTEM AND MEMORY TESTING METHOD
- Publication number 20250131974
- Publication date Apr 24, 2025
- NANYA TECHNOLOGY CORPORATION
- Chien Yu CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...
- Publication number 20250131970
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Massimo Sutera
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF
- Publication number 20250124996
- Publication date Apr 17, 2025
- WINBOND ELECTRONICS CORP.
- Chih-Chiang Lai
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE FOR CONTROLLING OPERATING POWER SUPPLIED TO WO...
- Publication number 20250124998
- Publication date Apr 17, 2025
- SK HYNIX INC.
- Byeong Cheol LEE
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY DEVICE INCLUDING WORDLINE LEAKAGE CURRENT DETECT...
- Publication number 20250124995
- Publication date Apr 17, 2025
- Samsung Electronics Co., Ltd.
- Buil Nam
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO GENERATION OF INTERNAL COMMMANDS
- Publication number 20250124999
- Publication date Apr 17, 2025
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING CIRCUIT FOR A MEMORY DEVICE
- Publication number 20250118385
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Chunqiang Weng
- G11 - INFORMATION STORAGE
Information Patent Application
METADATA STORAGE AT A MEMORY DEVICE
- Publication number 20250118388
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BUILT-IN SELF-TEST WITH ADDRESS SKIPPING TRIM SEARCH
- Publication number 20250111883
- Publication date Apr 3, 2025
- Siemens Industry Software Inc.
- Jongsin Yun
- G11 - INFORMATION STORAGE
Information Patent Application
HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY
- Publication number 20250111884
- Publication date Apr 3, 2025
- Micron Technology, Inc.
- Tomoko Ogura Iwasaki
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND AN OPERATING METHOD THEREOF
- Publication number 20250104788
- Publication date Mar 27, 2025
- Yangtze Memory Technologies Co., Ltd.
- Shuai ZHANG
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-READ DATA INTEGRITY SCAN IN A MEMORY SUB-SYSTEM
- Publication number 20250104789
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage Ramp Memory Calibration
- Publication number 20250104790
- Publication date Mar 27, 2025
- Apple Inc.
- Robert E. Jeter
- G11 - INFORMATION STORAGE
Information Patent Application
READ DESTRUCTIVE MEMORY WEAR LEVELING SYSTEM
- Publication number 20250104793
- Publication date Mar 27, 2025
- SEAGATE TECHNOLOGY LLC
- Jon D. TRANTHAM
- G11 - INFORMATION STORAGE
Information Patent Application
DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE
- Publication number 20250104743
- Publication date Mar 27, 2025
- SK HYNIX INC.
- Ie Ryung PARK
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS INCLUDING BTI CONTROLLER
- Publication number 20250104792
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- YASUSHI MATSUBARA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY
- Publication number 20250095762
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER AND OUTPUT LATCH CIRCUIT FOR TESTING
- Publication number 20250087291
- Publication date Mar 13, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- Hua-Hsin Yu
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE DSP GENERATION OF READ THRESHOLDS FOR GAUSSIAN AND NON-GAU...
- Publication number 20250087288
- Publication date Mar 13, 2025
- Beijing Tenafe Electronic Technology Co., Ltd.
- Yingquan Wu
- G11 - INFORMATION STORAGE

Built-in arrangements for testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory device including sense amplifying circuit

Memory device and operating method of the memory device

Reconfigurable MBIST method based on adaptive march algorithm

System and method for testing memory device

In-situ detection of anomalies in integrated circuits using machine...

Volatile memory devices and methods of operating same to improve re...

Configurable testing and repair system for non-volatile memory

Interactive DRAM signal analyzer and method of analyzing and calibr...

Semiconductor memory devices that support enhanced data recovery op...

Configurable scan chain architecture for multi-port memory

Memory system including a sub-controller and operating method of th...

System and method for testing a non-volatile memory

Adjusting memory power consumption

Memory device, memory device test method, and test system

Memory interface and semiconductor memory device and semiconductor...

Non-volatile memory with layout adaptive problematic word line dete...

Built-in self-test burst patterns based on architecture of memory

Test circuit and receiving circuit having test function

Test circuit for detecting word line defect and semiconductor appar...

Bit retiring to mitigate bit errors

Component die validation built-in self-test (VBIST) engine

Memory system

Memory BIST circuit and method

Memory device interface and method

Memory device and method for operating the same including setting a...

System and method for testing memory device

Vera detection method to catch erase fail

Memory device configured to reduce degradation of adjacent word lin...

Methods and systems for improving ECC operation of memories

Built-in self-test circuit for row hammering in memory

Patents Applicationslast 30 patents

MEMORY REPAIR CIRCUIT, A MEMORY REPAIR METHOD, AND A MEMORY DEVICE

LASER DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

ACTIVATION FUNCTIONS FOR ARTIFICIAL INTELLIGENCE OPERATIONS

INTERACTIVE DRAM SIGNAL ANALYZER AND METHOD OF ANALYZING AND CALIBR...

STORAGE DEVICE AND OPERATING METHOD THEREOF

TEST MODE STATE MACHINE FOR A MEMORY DEVICE

MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND SEMICONDUCTO...

SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION

SCHEME TO FETCH OPTIMAL READ PARAMETERS BY SKIPPING INVALID WORDLINES

METHOD FOR ISOLATING FAULTY NAND TEMPERATURE SENSOR

STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS

MEMORY TESTING SYSTEM AND MEMORY TESTING METHOD

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...

SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF

SEMICONDUCTOR DEVICE FOR CONTROLLING OPERATING POWER SUPPLIED TO WO...

NONVOLATILE MEMORY DEVICE INCLUDING WORDLINE LEAKAGE CURRENT DETECT...

SEMICONDUCTOR DEVICES RELATED TO GENERATION OF INTERNAL COMMMANDS

TESTING CIRCUIT FOR A MEMORY DEVICE

METADATA STORAGE AT A MEMORY DEVICE

MEMORY BUILT-IN SELF-TEST WITH ADDRESS SKIPPING TRIM SEARCH

HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY

MEMORY SYSTEM AND AN OPERATING METHOD THEREOF

DUAL-READ DATA INTEGRITY SCAN IN A MEMORY SUB-SYSTEM

Voltage Ramp Memory Calibration

READ DESTRUCTIVE MEMORY WEAR LEVELING SYSTEM

DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE

APPARATUS INCLUDING BTI CONTROLLER

MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY

SENSE AMPLIFIER AND OUTPUT LATCH CIRCUIT FOR TESTING

ADAPTIVE DSP GENERATION OF READ THRESHOLDS FOR GAUSSIAN AND NON-GAU...