Built-in arrangements for testing

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G11C29/12

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GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/12Built-in arrangements for testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Testability circuit and read and write path decoupling circuit of SRAM
- Patent number 12,260,924
- Issue date Mar 25, 2025
- Shanghai Huali Integrated Circuit Corporation
- Zhenan Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Data integrity check in non-volatile storage
- Patent number 12,260,925
- Issue date Mar 25, 2025
- SanDisk Technologies, Inc.
- Sugandha Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Loopback datapath for clock quality detection
- Patent number 12,260,926
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Matthew Alan Prather
- G11 - INFORMATION STORAGE
Information Patent Grant
Die-based high and low priority error queues
- Patent number 12,260,927
- Issue date Mar 25, 2025
- Kioxia Corporation
- Gyan Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile memory device and method of operating nonvolatile memory
- Patent number 12,260,923
- Issue date Mar 25, 2025
- Samsung Electronics Co., Ltd.
- Hyunee Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Data storage device and method for runtime exclusive—or zoning duri...
- Patent number 12,254,936
- Issue date Mar 18, 2025
- SanDisk Technologies, Inc.
- Pawan Negi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device interface and method
- Patent number 12,253,943
- Issue date Mar 18, 2025
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and method for performing test
- Patent number 12,254,937
- Issue date Mar 18, 2025
- SK hynix Inc.
- Choung Ki Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with serial and parallel testing structure for sensin...
- Patent number 12,254,938
- Issue date Mar 18, 2025
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit, test method and memory
- Patent number 12,254,941
- Issue date Mar 18, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Jianyong Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory repair circuit, a memory repair method, and a memory device
- Patent number 12,249,384
- Issue date Mar 11, 2025
- Samsung Electronics Co., Ltd.
- Hyunseok Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface circuit, memory controller and method for calibrating sig...
- Patent number 12,249,385
- Issue date Mar 11, 2025
- Silicon Motion, Inc.
- Fu-Jen Shih
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory, memory system and operation method of memory system
- Patent number 12,249,386
- Issue date Mar 11, 2025
- SK Hynix Inc.
- Munseon Jang
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage system and method for proactive die retirement by fatal wor...
- Patent number 12,243,605
- Issue date Mar 4, 2025
- SanDisk Technologies, Inc.
- Xuan Tian
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, device, and circuit for high-speed memories
- Patent number 12,243,602
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jaspal Singh Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Indicating a status of a memory built-in self-test
- Patent number 12,243,607
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed test of functional memory interface logic in devices
- Patent number 12,243,603
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Scannable memory array and a method for scanning memory
- Patent number 12,243,604
- Issue date Mar 4, 2025
- SambaNova Systems, Inc.
- Thomas Ziaja
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh rate selection for a memory built-in self-test
- Patent number 12,237,031
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test circuits for memory systems having multiple chan...
- Patent number 12,230,345
- Issue date Feb 18, 2025
- Samsung Electronics Co., Ltd.
- Jaewon Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line layer dependent stress and screen voltage
- Patent number 12,230,344
- Issue date Feb 18, 2025
- SanDisk Technologies, Inc.
- Yidan Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point memory read technique to mitigate drift errors
- Patent number 12,230,346
- Issue date Feb 18, 2025
- Intel Corporation
- Hemant P. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Laser detecting circuit and semiconductor apparatus including the same
- Patent number 12,230,588
- Issue date Feb 18, 2025
- Samsung Electronics Co., Ltd.
- Cheolhwan Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller to detect malfunctioning address of memory device
- Patent number 12,230,350
- Issue date Feb 18, 2025
- RAMBUS INC.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and information processing system for testing storage...
- Patent number 12,224,027
- Issue date Feb 11, 2025
- Kioxia Corporation
- Masayoshi Sato
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array test structure and method of forming the same
- Patent number 12,217,826
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Han Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 12,217,811
- Issue date Feb 4, 2025
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory testing system and memory testing method
- Patent number 12,217,815
- Issue date Feb 4, 2025
- NANYA TECHNOLOGY CORPORATION
- Chien Yu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit and method for reading data from a memory device durin...
- Patent number 12,211,570
- Issue date Jan 28, 2025
- Realtek Semiconductor Corp.
- Li-Wei Deng
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst indicator systems and methods
- Patent number 12,211,573
- Issue date Jan 28, 2025
- Micron Technology, Inc.
- Kai Wang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM AND AN OPERATING METHOD THEREOF
- Publication number 20250104788
- Publication date Mar 27, 2025
- Yangtze Memory Technologies Co., Ltd.
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-READ DATA INTEGRITY SCAN IN A MEMORY SUB-SYSTEM
- Publication number 20250104789
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- G11 - INFORMATION STORAGE
Information Patent Application
DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE
- Publication number 20250104743
- Publication date Mar 27, 2025
- SK HYNIX INC.
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage Ramp Memory Calibration
- Publication number 20250104790
- Publication date Mar 27, 2025
- Apple Inc.
- G11 - INFORMATION STORAGE
Information Patent Application
READ DESTRUCTIVE MEMORY WEAR LEVELING SYSTEM
- Publication number 20250104793
- Publication date Mar 27, 2025
- SEAGATE TECHNOLOGY LLC
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS INCLUDING BTI CONTROLLER
- Publication number 20250104792
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY
- Publication number 20250095762
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER AND OUTPUT LATCH CIRCUIT FOR TESTING
- Publication number 20250087291
- Publication date Mar 13, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- Hua-Hsin Yu
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE DSP GENERATION OF READ THRESHOLDS FOR GAUSSIAN AND NON-GAU...
- Publication number 20250087288
- Publication date Mar 13, 2025
- Beijing Tenafe Electronic Technology Co., Ltd.
- Yingquan Wu
- G11 - INFORMATION STORAGE
Information Patent Application
MBIST CONTROL CIRCUIT AND METHOD, MEMORY
- Publication number 20250078945
- Publication date Mar 6, 2025
- CXMT Corporation
- Jingwei CHENG
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR INITIALIZING MEMORY ERROR CORRECTION
- Publication number 20250078948
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Kai Wang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20250078946
- Publication date Mar 6, 2025
- RENESAS ELECTRONICS CORPORATION
- Tomohiro MIURA
- G11 - INFORMATION STORAGE
Information Patent Application
IMAGE DISPLAY DEVICE
- Publication number 20250078944
- Publication date Mar 6, 2025
- LG ELECTRONICS INC.
- Wonsang JEONG
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20250069678
- Publication date Feb 27, 2025
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND OPERATION METHOD THEREOF
- Publication number 20250069639
- Publication date Feb 27, 2025
- SK HYNIX INC.
- Sang Woo YOON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC DEVICE AND SYSTEM AND METHODS FOR DEFINITION AND CONFIGURATIO...
- Publication number 20250061958
- Publication date Feb 20, 2025
- MENTA
- Clément AYME
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MEMORY TEST SYSTEM THEREOF
- Publication number 20250061957
- Publication date Feb 20, 2025
- Samsung Electronics Co., Ltd.
- Seokwoo Lee
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING METHOD AND MEMORY MODULE UNDER TEST
- Publication number 20250046391
- Publication date Feb 6, 2025
- NANYA TECHNOLOGY CORPORATION
- Wei-Chun CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE RAMP RATE MONITOR FOR EARLY DETECTION OF DEFECT ACTIVATION
- Publication number 20250046390
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Fulvio Rori
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER FOR CONTROLLING BACKGROUND OPERATION AND OPERATIO...
- Publication number 20250037779
- Publication date Jan 30, 2025
- Samsung Electronics Co., Ltd.
- Sangsoo Cha
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC FUSE DEVICE AND OPERATION METHOD THEREOF
- Publication number 20250037780
- Publication date Jan 30, 2025
- Faraday Technology Corp.
- Chi-Chou Huang
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20250031455
- Publication date Jan 23, 2025
- Advantest Corporation
- Shinji SUGATANI
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST
- Publication number 20250022526
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Che Tsai
- G11 - INFORMATION STORAGE
Information Patent Application
HEAT GENERATION CONTROL FOR MEMORY SYSTEM EVALUATION
- Publication number 20250022528
- Publication date Jan 16, 2025
- Micron Technology, Inc.
- Natalia Tarazona Cordoba
- G01 - MEASURING TESTING
Information Patent Application
MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF
- Publication number 20250022524
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- YOUNGSAN KANG
- G11 - INFORMATION STORAGE
Information Patent Application
DATA TRANSFER OVER AN INTERCONNECT BETWEEN DIES OF A THREE-DIMENSIO...
- Publication number 20250022527
- Publication date Jan 16, 2025
- Intel Corporation
- Santhosh Kumar Chandrakanthan
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE AND OPERATING METHOD OF CONTROLLER OF STORAGE DEVICE
- Publication number 20250022525
- Publication date Jan 16, 2025
- SK HYNIX INC.
- Young Gyun KIM
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE DETERMINING DETERIORATION WORDLINE, AND METHOD OF OP...
- Publication number 20250014664
- Publication date Jan 9, 2025
- Samsung Electronics Co., Ltd.
- Minji Cho
- G11 - INFORMATION STORAGE
Information Patent Application
TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE
- Publication number 20250014665
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Ivo Thomas Wambeke
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT
- Publication number 20250014667
- Publication date Jan 9, 2025
- ROHM CO., LTD.
- Daigo FUJIMURA
- G11 - INFORMATION STORAGE

Built-in arrangements for testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Testability circuit and read and write path decoupling circuit of SRAM

Data integrity check in non-volatile storage

Loopback datapath for clock quality detection

Die-based high and low priority error queues

Nonvolatile memory device and method of operating nonvolatile memory

Data storage device and method for runtime exclusive—or zoning duri...

Memory device interface and method

Semiconductor device and method for performing test

Memory device with serial and parallel testing structure for sensin...

Test circuit, test method and memory

Memory repair circuit, a memory repair method, and a memory device

Interface circuit, memory controller and method for calibrating sig...

Memory, memory system and operation method of memory system

Storage system and method for proactive die retirement by fatal wor...

Method, device, and circuit for high-speed memories

Indicating a status of a memory built-in self-test

At-speed test of functional memory interface logic in devices

Scannable memory array and a method for scanning memory

Refresh rate selection for a memory built-in self-test

Built-in self-test circuits for memory systems having multiple chan...

Word line layer dependent stress and screen voltage

Cross-point memory read technique to mitigate drift errors

Laser detecting circuit and semiconductor apparatus including the same

Controller to detect malfunctioning address of memory device

Memory system and information processing system for testing storage...

Memory array test structure and method of forming the same

Programmable logic device with design for test functionality

Memory testing system and memory testing method

Test circuit and method for reading data from a memory device durin...

Burst indicator systems and methods

Patents Applicationslast 30 patents

MEMORY SYSTEM AND AN OPERATING METHOD THEREOF

DUAL-READ DATA INTEGRITY SCAN IN A MEMORY SUB-SYSTEM

DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE

Voltage Ramp Memory Calibration

READ DESTRUCTIVE MEMORY WEAR LEVELING SYSTEM

APPARATUS INCLUDING BTI CONTROLLER

MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY

SENSE AMPLIFIER AND OUTPUT LATCH CIRCUIT FOR TESTING

ADAPTIVE DSP GENERATION OF READ THRESHOLDS FOR GAUSSIAN AND NON-GAU...

MBIST CONTROL CIRCUIT AND METHOD, MEMORY

TECHNIQUES FOR INITIALIZING MEMORY ERROR CORRECTION

MEMORY DEVICE

IMAGE DISPLAY DEVICE

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY AND OPERATION METHOD THEREOF

LOGIC DEVICE AND SYSTEM AND METHODS FOR DEFINITION AND CONFIGURATIO...

MEMORY DEVICE AND MEMORY TEST SYSTEM THEREOF

TESTING METHOD AND MEMORY MODULE UNDER TEST

WORDLINE RAMP RATE MONITOR FOR EARLY DETECTION OF DEFECT ACTIVATION

MEMORY CONTROLLER FOR CONTROLLING BACKGROUND OPERATION AND OPERATIO...

ELECTRONIC FUSE DEVICE AND OPERATION METHOD THEREOF

THREE-DIMENSIONAL DEVICE AND MANUFACTURING METHOD THEREOF

CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST

HEAT GENERATION CONTROL FOR MEMORY SYSTEM EVALUATION

MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF

DATA TRANSFER OVER AN INTERCONNECT BETWEEN DIES OF A THREE-DIMENSIO...

STORAGE DEVICE AND OPERATING METHOD OF CONTROLLER OF STORAGE DEVICE

STORAGE DEVICE DETERMINING DETERIORATION WORDLINE, AND METHOD OF OP...

TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE

MEMORY CIRCUIT