Clock generating, synchronizing or distributing circuits within memory device

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GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/222Clock generating, synchronizing or distributing circuits within memory device

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Patents Grantslast 30 patents

Information Patent Grant
Memory system using asymmetric source-synchronous clocking
- Patent number 12,228,961
- Issue date Feb 18, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for receiving strobe signal
- Patent number 12,231,100
- Issue date Feb 18, 2025
- Electronics and Telecommunications Research Institute
- Yi-Gyeong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling memory module clock buffer power in a system with dual...
- Patent number 12,230,360
- Issue date Feb 18, 2025
- Dell Products L.P.
- Isaac Q. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Device with synchronous output
- Patent number 12,230,357
- Issue date Feb 18, 2025
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Acceleration of in-memory-compute arrays
- Patent number 12,230,361
- Issue date Feb 18, 2025
- Apple Inc.
- Paolo Di Febbo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory system, and operating method of memory system
- Patent number 12,230,356
- Issue date Feb 18, 2025
- Samsung Electronics Co., Ltd.
- Sun Young Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with programmable data-to-clock ratio
- Patent number 12,230,362
- Issue date Feb 18, 2025
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device related to calibrating termination resistance
- Patent number 12,224,747
- Issue date Feb 11, 2025
- SK hynix Inc.
- Chae Sung Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Counter circuit
- Patent number 12,217,820
- Issue date Feb 4, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Yinchuan Gu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for supporting command bus training mode and method o...
- Patent number 12,217,823
- Issue date Feb 4, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Finite time counting period counting of infinite data streams
- Patent number 12,217,824
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Edmund Gieske
- G11 - INFORMATION STORAGE
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal generator for controlling timing of signal in memory device
- Patent number 12,211,586
- Issue date Jan 28, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiu-Li Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout for dual in-line memory to support 128-byte cache line proce...
- Patent number 12,211,577
- Issue date Jan 28, 2025
- Tachyum Ltd.
- Radoslav Danilak
- G11 - INFORMATION STORAGE
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data-buffer controller/control-signal redriver
- Patent number 12,211,583
- Issue date Jan 28, 2025
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller, memory system and operating method of memory system
- Patent number 12,205,662
- Issue date Jan 21, 2025
- SK Hynix Inc.
- Young Ook Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipe latch circuit, operating method thereof, and semiconductor mem...
- Patent number 12,205,666
- Issue date Jan 21, 2025
- SK hynix Inc.
- Bo Kyeom Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Read data strobe path having variation compensation and delay lines
- Patent number 12,205,673
- Issue date Jan 21, 2025
- Cadence Design Systems, Inc.
- Hari Anand Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device related to calibrating a termination resistance
- Patent number 12,198,784
- Issue date Jan 14, 2025
- SK hynix Inc.
- Jung Taek You
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods including memory commands for semiconductor...
- Patent number 12,197,355
- Issue date Jan 14, 2025
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, memory device, and method for multi-phase clock training
- Patent number 12,198,783
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Taegook Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and memory system including the same
- Patent number 12,190,995
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Byunghoon Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Command processing circuit and data processing circuit
- Patent number 12,190,992
- Issue date Jan 7, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liping Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Single port memory with multiple memory operations per clock cycle
- Patent number 12,190,994
- Issue date Jan 7, 2025
- Xilinx, Inc.
- Kumar Rahul
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deferred fractional memory row activation
- Patent number 12,190,990
- Issue date Jan 7, 2025
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch circuit and memory device
- Patent number 12,184,285
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TIMING-DRIFT CALIBRATION
- Publication number 20250054561
- Publication date Feb 13, 2025
- Rambus Inc.
- Yohan U. Frans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
- Publication number 20250054526
- Publication date Feb 13, 2025
- SK HYNIX INC.
- Chan Keun KWON
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK DISTRIBUTION NETWORK, AND SEMICONDUCTOR APPARATUS AND SEMICON...
- Publication number 20250053190
- Publication date Feb 13, 2025
- SK HYNIX INC.
- Ji Hyo KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Generation for Timing Communications with Ranks of Memory Dev...
- Publication number 20250053524
- Publication date Feb 13, 2025
- Rambus Inc.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICES
- Publication number 20250054563
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Sehwan Park
- G11 - INFORMATION STORAGE
Information Patent Application
POWER EFFICIENT UNMATCHED DATA PATH ARCHITECTURE FOR NON-VOLATILE M...
- Publication number 20250046351
- Publication date Feb 6, 2025
- Western Digital Technologies, Inc.
- Abhishek Singhania
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE FOR GENERATING A DELAY SIGNAL, AND A METHOD OF OPERA...
- Publication number 20250046354
- Publication date Feb 6, 2025
- Samsung Electronics Co., Ltd.
- LAESANG JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE RELATED TO SIGNAL INTEGRITY OF CLOCK
- Publication number 20250029643
- Publication date Jan 23, 2025
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
- Publication number 20250029641
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuits And Methods For Generating Adjustable Signal Pulses That C...
- Publication number 20250022495
- Publication date Jan 16, 2025
- Altera Corporation
- Wee Leam Teoh
- G11 - INFORMATION STORAGE
Information Patent Application
DUTY CYCLE CORRECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND...
- Publication number 20250023557
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- WOOSEUK OH
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...
- Publication number 20250022496
- Publication date Jan 16, 2025
- Lodestar Licensing Group LLC
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LEAKAGE COMPENSATED DYNAMIC LATCH
- Publication number 20250006234
- Publication date Jan 2, 2025
- Intel Corporation
- Ganesan Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
HOST APPARATUS AND EXTENSION DEVICE
- Publication number 20240428843
- Publication date Dec 26, 2024
- KIOXIA Corporation
- Akihisa FUJIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND CONTROL METHOD THEREFOR
- Publication number 20240428878
- Publication date Dec 26, 2024
- CXMT Corporation
- Zequn HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING
- Publication number 20240428835
- Publication date Dec 26, 2024
- Rambus Inc.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK
- Publication number 20240420749
- Publication date Dec 19, 2024
- Realtek Semiconductor Corp.
- WEI-CHEN LIU
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME
- Publication number 20240420754
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- DAE-SIK MOON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE
- Publication number 20240412764
- Publication date Dec 12, 2024
- Samsung Electronics Co., Ltd.
- Jueon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME
- Publication number 20240412767
- Publication date Dec 12, 2024
- Samsung Electronics Co., LTD
- CHANHEE PARK
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-Charger Circuit of Memory Device and Methods For Operating The...
- Publication number 20240412766
- Publication date Dec 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Masaya Hamada
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD
- Publication number 20240402936
- Publication date Dec 5, 2024
- PHISON ELECTRONICS CORP.
- Cheng-Jui Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...
- Publication number 20240404570
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- Ki-Seok PARK
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION
- Publication number 20240404568
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Riccardo ZURLA
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
- Publication number 20240404571
- Publication date Dec 5, 2024
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE

Clock generating, synchronizing or distributing circuits within memory device

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory system using asymmetric source-synchronous clocking

Apparatus and method for receiving strobe signal

Controlling memory module clock buffer power in a system with dual...

Device with synchronous output

Acceleration of in-memory-compute arrays

Memory device, memory system, and operating method of memory system

Memory component with programmable data-to-clock ratio

Semiconductor device related to calibrating termination resistance

Counter circuit

Memory device for supporting command bus training mode and method o...

Finite time counting period counting of infinite data streams

Atomic compare and swap in a coherent cache system

Signal generator for controlling timing of signal in memory device

Layout for dual in-line memory to support 128-byte cache line proce...

Aggressive write flush scheme for a victim cache

Data-buffer controller/control-signal redriver

Controller, memory system and operating method of memory system

Pipe latch circuit, operating method thereof, and semiconductor mem...

Read data strobe path having variation compensation and delay lines

Methods and apparatus to reduce bank pressure using aggressive writ...

Semiconductor device related to calibrating a termination resistance

Apparatuses and methods including memory commands for semiconductor...

Apparatus, memory device, and method for multi-phase clock training

Memory device and memory system including the same

Command processing circuit and data processing circuit

Single port memory with multiple memory operations per clock cycle

Fully pipelined read-modify-write support

Deferred fractional memory row activation

Latch circuit and memory device

Shared decoder circuit and method

Patents Applicationslast 30 patents

TIMING-DRIFT CALIBRATION

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

CLOCK DISTRIBUTION NETWORK, AND SEMICONDUCTOR APPARATUS AND SEMICON...

Clock Generation for Timing Communications with Ranks of Memory Dev...

GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICES

POWER EFFICIENT UNMATCHED DATA PATH ARCHITECTURE FOR NON-VOLATILE M...

STORAGE DEVICE FOR GENERATING A DELAY SIGNAL, AND A METHOD OF OPERA...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

MEMORY MODULE RELATED TO SIGNAL INTEGRITY OF CLOCK

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

Circuits And Methods For Generating Adjustable Signal Pulses That C...

DUTY CYCLE CORRECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND...

APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...

LEAKAGE COMPENSATED DYNAMIC LATCH

HOST APPARATUS AND EXTENSION DEVICE

MEMORY DEVICE AND CONTROL METHOD THEREFOR

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME

RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE

MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME

Pre-Charger Circuit of Memory Device and Methods For Operating The...

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD

MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...

IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION

LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST