Clock generating, synchronizing or distributing circuits within memory device

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G11C7/222

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GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/222Clock generating, synchronizing or distributing circuits within memory device

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Controller, memory system and operating method of memory system
- Patent number 12,205,662
- Issue date Jan 21, 2025
- SK Hynix Inc.
- Young Ook Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipe latch circuit, operating method thereof, and semiconductor mem...
- Patent number 12,205,666
- Issue date Jan 21, 2025
- SK hynix Inc.
- Bo Kyeom Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Read data strobe path having variation compensation and delay lines
- Patent number 12,205,673
- Issue date Jan 21, 2025
- Cadence Design Systems, Inc.
- Hari Anand Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device related to calibrating a termination resistance
- Patent number 12,198,784
- Issue date Jan 14, 2025
- SK hynix Inc.
- Jung Taek You
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods including memory commands for semiconductor...
- Patent number 12,197,355
- Issue date Jan 14, 2025
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, memory device, and method for multi-phase clock training
- Patent number 12,198,783
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Taegook Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and memory system including the same
- Patent number 12,190,995
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Byunghoon Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Command processing circuit and data processing circuit
- Patent number 12,190,992
- Issue date Jan 7, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liping Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Single port memory with multiple memory operations per clock cycle
- Patent number 12,190,994
- Issue date Jan 7, 2025
- Xilinx, Inc.
- Kumar Rahul
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deferred fractional memory row activation
- Patent number 12,190,990
- Issue date Jan 7, 2025
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch circuit and memory device
- Patent number 12,184,285
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with compensated word line access delay
- Patent number 12,183,420
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Si Hong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for write clock double data rate duty cycle corre...
- Patent number 12,183,427
- Issue date Dec 31, 2024
- Cadence Design Systems, Inc.
- Sachin Ramesh Gugwad
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method of operating the same
- Patent number 12,183,428
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on chip and application processor
- Patent number 12,174,683
- Issue date Dec 24, 2024
- Samsung Electronics Co., Ltd.
- Junhee Yoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods employing asynchronous FIFO buffer with read...
- Patent number 12,176,064
- Issue date Dec 24, 2024
- Advanced Micro Devices, Inc.
- Richard Martin Born
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data receiving circuit, data receiving system, and memory device
- Patent number 12,176,055
- Issue date Dec 24, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Channel routing for simultaneous switching outputs
- Patent number 12,176,065
- Issue date Dec 24, 2024
- ATI Technologies ULC
- Xuan Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer configurations for communications between memory dies and a...
- Patent number 12,170,127
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Sujeet V. Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiving circuit, data receiving system and storage device
- Patent number 12,170,129
- Issue date Dec 17, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM non-clamping write driver with write assist
- Patent number 12,165,738
- Issue date Dec 10, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting margins of data signal and stora...
- Patent number 12,159,034
- Issue date Dec 3, 2024
- Huawei Technologies Co., Ltd.
- Yongyao Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock circuit, memory and method for manufacturing semiconductor st...
- Patent number 12,159,687
- Issue date Dec 3, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Meixiang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel and sub-channel throttling for memory controllers
- Patent number 12,154,657
- Issue date Nov 26, 2024
- Advanced Micro Devices, Inc.
- Kedarnath Balakrishnan
- G11 - INFORMATION STORAGE
Information Patent Grant
Data output control circuit and semiconductor device including the...
- Patent number 12,154,658
- Issue date Nov 26, 2024
- SK Hynix Inc.
- Kwang Soon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method of controlling a memory chip
- Patent number 12,154,659
- Issue date Nov 26, 2024
- Kioxia Corporation
- Shinya Koizumi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Circuits And Methods For Generating Adjustable Signal Pulses That C...
- Publication number 20250022495
- Publication date Jan 16, 2025
- Altera Corporation
- Wee Leam Teoh
- G11 - INFORMATION STORAGE
Information Patent Application
DUTY CYCLE CORRECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND...
- Publication number 20250023557
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- WOOSEUK OH
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...
- Publication number 20250022496
- Publication date Jan 16, 2025
- Lodestar Licensing Group LLC
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LEAKAGE COMPENSATED DYNAMIC LATCH
- Publication number 20250006234
- Publication date Jan 2, 2025
- Intel Corporation
- Ganesan Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
HOST APPARATUS AND EXTENSION DEVICE
- Publication number 20240428843
- Publication date Dec 26, 2024
- KIOXIA Corporation
- Akihisa FUJIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND CONTROL METHOD THEREFOR
- Publication number 20240428878
- Publication date Dec 26, 2024
- CXMT Corporation
- Zequn HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING
- Publication number 20240428835
- Publication date Dec 26, 2024
- Rambus Inc.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK
- Publication number 20240420749
- Publication date Dec 19, 2024
- Realtek Semiconductor Corp.
- WEI-CHEN LIU
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME
- Publication number 20240420754
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- DAE-SIK MOON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE
- Publication number 20240412764
- Publication date Dec 12, 2024
- Samsung Electronics Co., Ltd.
- Jueon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME
- Publication number 20240412767
- Publication date Dec 12, 2024
- Samsung Electronics Co., LTD
- CHANHEE PARK
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-Charger Circuit of Memory Device and Methods For Operating The...
- Publication number 20240412766
- Publication date Dec 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Masaya Hamada
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD
- Publication number 20240402936
- Publication date Dec 5, 2024
- PHISON ELECTRONICS CORP.
- Cheng-Jui Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...
- Publication number 20240404570
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- Ki-Seok PARK
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION
- Publication number 20240404568
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Riccardo ZURLA
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
- Publication number 20240404571
- Publication date Dec 5, 2024
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND MET...
- Publication number 20240404572
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- HYUNGJIN KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING READ AND WRITE OF MEMORY CELLS
- Publication number 20240395297
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Ferdinando Bedeschi
- G11 - INFORMATION STORAGE
Information Patent Application
JITTER REDUCTION IN MIXED-SIGNAL PROCESSING CIRCUITS
- Publication number 20240395295
- Publication date Nov 28, 2024
- ADVANCED MICRO DEVICES, INC.
- Srikanth Reddy Gruddanti
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS
- Publication number 20240395296
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20240395298
- Publication date Nov 28, 2024
- Samsung Electronics Co., Ltd.
- BAEK JIN LIM
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL SKEW IN SOURCE-SYNCHRONOUS SYSTEM
- Publication number 20240395310
- Publication date Nov 28, 2024
- Rambus Inc.
- Shahram NIKOUKARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...
- Publication number 20240386928
- Publication date Nov 21, 2024
- Lodestar Licensing Group LLC
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTR...
- Publication number 20240379141
- Publication date Nov 14, 2024
- Samsung Electronics Co., Ltd.
- TONGSUNG KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF VOLTAGE CALIBRATION AND APPARATUS THEREOF, MEMORY AND MEM...
- Publication number 20240379135
- Publication date Nov 14, 2024
- Yangtze Memory Technologies Co., Ltd.
- Tianyi YE
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for an Internal Clock Tree Structure in a Memor...
- Publication number 20240371421
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
- Publication number 20240370390
- Publication date Nov 7, 2024
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FO...
- Publication number 20240371418
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaspal Singh Shah
- G11 - INFORMATION STORAGE

Clock generating, synchronizing or distributing circuits within memory device

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Controller, memory system and operating method of memory system

Pipe latch circuit, operating method thereof, and semiconductor mem...

Read data strobe path having variation compensation and delay lines

Semiconductor device related to calibrating a termination resistance

Methods and apparatus to reduce bank pressure using aggressive writ...

Apparatuses and methods including memory commands for semiconductor...

Apparatus, memory device, and method for multi-phase clock training

Memory device and memory system including the same

Command processing circuit and data processing circuit

Single port memory with multiple memory operations per clock cycle

Fully pipelined read-modify-write support

Deferred fractional memory row activation

Latch circuit and memory device

Shared decoder circuit and method

Memory array with compensated word line access delay

System and method for write clock double data rate duty cycle corre...

Memory circuit and method of operating the same

Methods and apparatus for allocation in a victim cache system

System on chip and application processor

Apparatus and methods employing asynchronous FIFO buffer with read...

Data receiving circuit, data receiving system, and memory device

Channel routing for simultaneous switching outputs

Buffer configurations for communications between memory dies and a...

Data receiving circuit, data receiving system and storage device

SRAM non-clamping write driver with write assist

Method and apparatus for detecting margins of data signal and stora...

Clock circuit, memory and method for manufacturing semiconductor st...

Channel and sub-channel throttling for memory controllers

Data output control circuit and semiconductor device including the...

Memory system and method of controlling a memory chip

Patents Applicationslast 30 patents

Circuits And Methods For Generating Adjustable Signal Pulses That C...

DUTY CYCLE CORRECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND...

APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...

LEAKAGE COMPENSATED DYNAMIC LATCH

HOST APPARATUS AND EXTENSION DEVICE

MEMORY DEVICE AND CONTROL METHOD THEREFOR

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

MEMORY CLOCK CONTROL CIRCUIT AND METHOD FOR CONTROLLING MEMORY CLOCK

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME

RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE

MULTI-BIT CELL AND MULTI-BIT CELL ARRAY INCLUDING THE SAME

Pre-Charger Circuit of Memory Device and Methods For Operating The...

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD

MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...

IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION

LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST

APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND MET...

METHODS AND SYSTEMS FOR IMPROVING READ AND WRITE OF MEMORY CELLS

JITTER REDUCTION IN MIXED-SIGNAL PROCESSING CIRCUITS

SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS

SEMICONDUCTOR DEVICE

SIGNAL SKEW IN SOURCE-SYNCHRONOUS SYSTEM

APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPRO...

MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTR...

METHOD OF VOLTAGE CALIBRATION AND APPARATUS THEREOF, MEMORY AND MEM...

Systems and Methods for an Internal Clock Tree Structure in a Memor...

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE

CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FO...