Combinations of a plurality of arrangements

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CPC
H01L2224/25177

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/25177Combinations of a plurality of arrangements

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device package
- Patent number 11,830,798
- Issue date Nov 28, 2023
- Advanced Semiconductor Engineering, Inc.
- You-Lung Yen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bridged fanout chiplet connectivity
- Patent number 11,658,123
- Issue date May 23, 2023
- Advanced Micro Devices, Inc.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing semiconductor package with connection stru...
- Patent number 11,532,587
- Issue date Dec 20, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien-Hsun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing semiconductor package with connection stru...
- Patent number 10,916,519
- Issue date Feb 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien-Hsun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged chip and signal transmission method based on packaged chip
- Patent number 10,490,506
- Issue date Nov 26, 2019
- Huawei Technologies Co., Ltd.
- Chih Chiang Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assembly tolerant to misplacement of microelectroni...
- Patent number 8,698,323
- Issue date Apr 15, 2014
- Invensas Corporation
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,653,639
- Issue date Feb 18, 2014
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite layered chip package
- Patent number 8,426,979
- Issue date Apr 23, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,358,015
- Issue date Jan 22, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for Manufacturing Semiconductor Package with Connection Stru...
- Publication number 20230122816
- Publication date Apr 20, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chien-Hsun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME
- Publication number 20220359478
- Publication date Nov 10, 2022
- SAMSUNG DISPLAY CO., LTD.
- Xinxing LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE PACKAGE
- Publication number 20220302008
- Publication date Sep 22, 2022
- Advanced Semiconductor Engineering, Inc.
- You-Lung YEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BRIDGED FANOUT CHIPLET CONNECTIVITY
- Publication number 20220102276
- Publication date Mar 31, 2022
- ADVANCED MICRO DEVICES, INC.
- RAHUL AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Manufacturing Semiconductor Package with Connection Stru...
- Publication number 20210167032
- Publication date Jun 3, 2021
- Taiwan Semiconductor Maufacturing Co., Ltd.
- Chien-Hsun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Packages and Method Forming Same
- Publication number 20190378809
- Publication date Dec 12, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien-Hsun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaged Chip and Signal Transmission Method Based on Packaged Chip
- Publication number 20180190590
- Publication date Jul 5, 2018
- Huawei Technologies Co., Ltd
- Chih Chiang Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONI...
- Publication number 20130334698
- Publication date Dec 19, 2013
- Invensas Corporation
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE LAYERED CHIP PACKAGE
- Publication number 20130020723
- Publication date Jan 24, 2013
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120313260
- Publication date Dec 13, 2012
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120313259
- Publication date Dec 13, 2012
- SAE Magnetics (H.K.) Ltd.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS

Combinations of a plurality of arrangements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor device package

Hybrid bridged fanout chiplet connectivity

Method for manufacturing semiconductor package with connection stru...

Method for manufacturing semiconductor package with connection stru...

Packaged chip and signal transmission method based on packaged chip

Microelectronic assembly tolerant to misplacement of microelectroni...

Layered chip package and method of manufacturing same

Composite layered chip package

Layered chip package and method of manufacturing same

Patents Applicationslast 30 patents

Method for Manufacturing Semiconductor Package with Connection Stru...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME

SEMICONDUCTOR DEVICE PACKAGE

HYBRID BRIDGED FANOUT CHIPLET CONNECTIVITY

Method for Manufacturing Semiconductor Package with Connection Stru...

Semiconductor Packages and Method Forming Same

Packaged Chip and Signal Transmission Method Based on Packaged Chip

MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONI...

COMPOSITE LAYERED CHIP PACKAGE

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME