Comparators; Diagnosing the device under test

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G01R31/318566

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318566Comparators; Diagnosing the device under test

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus to inject errors in a memory block and validat...
- Patent number 12,164,401
- Issue date Dec 10, 2024
- NXP B.V.
- Umesh Pratap Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus to identify faults in processors
- Patent number 12,085,610
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Lockstep comparators and related methods
- Patent number 12,025,659
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using scan chains to read out data from integrated sensors during s...
- Patent number 11,921,160
- Issue date Mar 5, 2024
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,899,064
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Core and interface scan testing architecture and methodology
- Patent number 11,879,942
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Banadappa Shivaray
- G01 - MEASURING TESTING
Information Patent Grant
Diagnostic apparatus
- Patent number 11,876,670
- Issue date Jan 16, 2024
- Nippon Telegraph and Telephone Corporation
- Takuya Oda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test method for control chip and related device
- Patent number 11,867,758
- Issue date Jan 9, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Chuanqi Shi
- G11 - INFORMATION STORAGE
Information Patent Grant
Stimulated circuits and fault testing methods
- Patent number 11,852,685
- Issue date Dec 26, 2023
- Hamilton Sundstrand Corporation
- Christopher Blazer
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 11,782,092
- Issue date Oct 10, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Self diagnostic apparatus for electronic device
- Patent number 11,686,772
- Issue date Jun 27, 2023
- PHOSPHIL INC.
- Byung Kyu Kim
- G01 - MEASURING TESTING
Information Patent Grant
Scalable scan architecture for multi-circuit block arrays
- Patent number 11,639,962
- Issue date May 2, 2023
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for monitoring data and timing signals in integra...
- Patent number 11,635,465
- Issue date Apr 25, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Rohit Goel
- G01 - MEASURING TESTING
Information Patent Grant
Controller structural testing with automated test vectors
- Patent number 11,598,808
- Issue date Mar 7, 2023
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal path monitor
- Patent number 11,561,257
- Issue date Jan 24, 2023
- ALLEGRO MICROSYSTEMS, LLC
- Ezequiel Rubinsztain
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,549,984
- Issue date Jan 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit
- Patent number 11,519,962
- Issue date Dec 6, 2022
- Realtek Semiconductor Corporation
- Jeong-Fa Sheu
- G01 - MEASURING TESTING
Information Patent Grant
System and method for facilitating built-in self-test of system-on-...
- Patent number 11,513,153
- Issue date Nov 29, 2022
- NXP USA, INC.
- Rohan Poudel
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing a circuit system and a circuit system thereof
- Patent number 11,506,710
- Issue date Nov 22, 2022
- Realtek Semiconductor Corporation
- Yen-Ju Lu
- G01 - MEASURING TESTING
Information Patent Grant
Testing memory elements using an internal testing interface
- Patent number 11,500,017
- Issue date Nov 15, 2022
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Side-channel signature based PCB authentication using JTAG architec...
- Patent number 11,480,614
- Issue date Oct 25, 2022
- University of Florida Research Foundation, Inc.
- Swarup Bhunia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for scan dump of latch array
- Patent number 11,443,823
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for row scannable latch array
- Patent number 11,443,822
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, method and system of error detection and correction in mult...
- Patent number 11,385,288
- Issue date Jul 12, 2022
- STMicroelectronics S.A.
- Ricardo Gomez Gomez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic enhancement for multiple instances of identical structures
- Patent number 11,378,623
- Issue date Jul 5, 2022
- International Business Machines Corporation
- Steven Michael Douskey
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, system and device to test a plurality of devices by compari...
- Patent number 11,353,508
- Issue date Jun 7, 2022
- STMicroelectronics S.A.
- Ricardo Gomez Gomez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems and apparatus for in-field testing for generic dia...
- Patent number 11,335,428
- Issue date May 17, 2022
- Intel Corporation
- Asad Azam
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STORAGE SYSTEM AND AN OPERATING METHOD THEREOF
- Publication number 20240353486
- Publication date Oct 24, 2024
- Samsung Electronics Co., Ltd.
- Ganggyu LEE
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS
- Publication number 20240345160
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20240133951
- Publication date Apr 25, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION THROUGH PIN DATA ENCODING
- Publication number 20230375617
- Publication date Nov 23, 2023
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
- Publication number 20230314506
- Publication date Oct 5, 2023
- STMicroelectronics International N.V.
- Roberto Colombo
- G01 - MEASURING TESTING
Information Patent Application
STIMULATED CIRCUITS AND FAULT TESTING METHODS
- Publication number 20230221369
- Publication date Jul 13, 2023
- HAMILTON SUNDSTRAND CORPORATION
- Christopher Blazer
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20230113905
- Publication date Apr 13, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR TESTING A CIRCUIT SYSTEM AND A CIRCUIT SYSTEM THEREOF
- Publication number 20220349940
- Publication date Nov 3, 2022
- REALTEK SEMICONDUCTOR CORPORATION
- Yen-Ju LU
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...
- Publication number 20220334181
- Publication date Oct 20, 2022
- NXP USA, Inc.
- Rohan Poudel
- G01 - MEASURING TESTING
Information Patent Application
SIGNAL PATH MONITOR
- Publication number 20220196739
- Publication date Jun 23, 2022
- ALLEGRO MICROSYSTEMS, LLC
- Ezequiel Rubinsztain
- G01 - MEASURING TESTING
Information Patent Application
SELF DIAGNOSTIC APPARATUS FOR ELECTRONIC DEVICE
- Publication number 20220137130
- Publication date May 5, 2022
- PhosPhil Inc.
- Byung Kyu KIM
- G01 - MEASURING TESTING
Information Patent Application
DEVICE AND METHOD FOR MONITORING DATA AND TIMING SIGNALS IN INTEGRA...
- Publication number 20220137133
- Publication date May 5, 2022
- STMicroelectronics International N.V.
- Rohit GOEL
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER STRUCTURAL TESTING WITH AUTOMATED TEST VECTORS
- Publication number 20210208199
- Publication date Jul 8, 2021
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Application
ERROR DETECTION AND CORRECTION
- Publication number 20210096183
- Publication date Apr 1, 2021
- STMicroelectronics S.A.
- Ricardo GOMEZ GOMEZ
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER STRUCTURAL TESTING WITH AUTOMATED TEST VECTORS
- Publication number 20200191869
- Publication date Jun 18, 2020
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST METHOD AND APPARATUS
- Publication number 20200049766
- Publication date Feb 13, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
RAPID SCAN TESTING OF INTEGRATED CIRCUIT CHIPS
- Publication number 20190339326
- Publication date Nov 7, 2019
- SEAGATE TECHNOLOGY LLC
- Rajesh Maruti Bhagwat
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE AND FAILURE DIAGNOSIS METHOD
- Publication number 20190285696
- Publication date Sep 19, 2019
- Kabushiki Kaisha Toshiba
- Tomoyuki Maekawa
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR DETECTING AND ISOLATING INTERMITTENCE IN MULT...
- Publication number 20190257882
- Publication date Aug 22, 2019
- Universal Synaptics Corporation
- Patrick Kelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Reducing Messaging Requirements In Wireless Power De...
- Publication number 20190181698
- Publication date Jun 13, 2019
- Ossia Inc.
- Hatem Zeine
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Techniques For Leveraging Existing Components Of A Device For Wirel...
- Publication number 20190115792
- Publication date Apr 18, 2019
- Ossia Inc.
- Hatem Zeine
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Techniques For Selectively Powering Devices In Wireless Power Deliv...
- Publication number 20190074732
- Publication date Mar 7, 2019
- Ossia Inc.
- Hatem Zeine
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TEST RESPONSE COMPACTION SCHEME
- Publication number 20190041453
- Publication date Feb 7, 2019
- GLOBALFOUNDRIES INC.
- JAIDEV UDYAVAR SHENOY
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST METHOD AND APPARATUS
- Publication number 20190033369
- Publication date Jan 31, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Techniques For Scheduling Delivery Of Wireless Power In Wireless Po...
- Publication number 20180309329
- Publication date Oct 25, 2018
- Ossia Inc.
- Hatem Zeine
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCU...
- Publication number 20180275198
- Publication date Sep 27, 2018
- Kabushiki Kaisha Toshiba
- Tomoyuki Maekawa
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20180156867
- Publication date Jun 7, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING SYSTEM, METHOD AND APPARATUS
- Publication number 20180052202
- Publication date Feb 22, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD...
- Publication number 20180003771
- Publication date Jan 4, 2018
- Renesas Electronics Corporation
- Takuro NISHIKAWA
- G01 - MEASURING TESTING

Comparators; Diagnosing the device under test

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method and apparatus to inject errors in a memory block and validat...

Scan compression through pin data encoding

Methods and apparatus to identify faults in processors

Test access port architecture to facilitate multiple testing modes

Lockstep comparators and related methods

Single “A” latch with an array of “B” latches

Using scan chains to read out data from integrated sensors during s...

Scan architecture for interconnect testing in 3D integrated circuits

Core and interface scan testing architecture and methodology

Diagnostic apparatus

Test method for control chip and related device

Stimulated circuits and fault testing methods

Scan compression through pin data encoding

Self diagnostic apparatus for electronic device

Scalable scan architecture for multi-circuit block arrays

Device and method for monitoring data and timing signals in integra...

Controller structural testing with automated test vectors

Signal path monitor

Scan architecture for interconnect testing in 3D integrated circuits

Test circuit

System and method for facilitating built-in self-test of system-on-...

Method for testing a circuit system and a circuit system thereof

Testing memory elements using an internal testing interface

Side-channel signature based PCB authentication using JTAG architec...

Method and circuit for scan dump of latch array

Method and circuit for row scannable latch array

Device, method and system of error detection and correction in mult...

Diagnostic enhancement for multiple instances of identical structures

Method, system and device to test a plurality of devices by compari...

Methods, systems and apparatus for in-field testing for generic dia...

Patents Applicationslast 30 patents

STORAGE SYSTEM AND AN OPERATING METHOD THEREOF

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

SCAN COMPRESSION THROUGH PIN DATA ENCODING

PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

STIMULATED CIRCUITS AND FAULT TESTING METHODS

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

METHOD FOR TESTING A CIRCUIT SYSTEM AND A CIRCUIT SYSTEM THEREOF

SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...

SIGNAL PATH MONITOR

SELF DIAGNOSTIC APPARATUS FOR ELECTRONIC DEVICE

DEVICE AND METHOD FOR MONITORING DATA AND TIMING SIGNALS IN INTEGRA...

CONTROLLER STRUCTURAL TESTING WITH AUTOMATED TEST VECTORS

ERROR DETECTION AND CORRECTION

CONTROLLER STRUCTURAL TESTING WITH AUTOMATED TEST VECTORS

SCAN TEST METHOD AND APPARATUS

RAPID SCAN TESTING OF INTEGRATED CIRCUIT CHIPS

SEMICONDUCTOR DEVICE AND FAILURE DIAGNOSIS METHOD

METHOD AND SYSTEM FOR DETECTING AND ISOLATING INTERMITTENCE IN MULT...

Techniques For Reducing Messaging Requirements In Wireless Power De...

Techniques For Leveraging Existing Components Of A Device For Wirel...

Techniques For Selectively Powering Devices In Wireless Power Deliv...

TEST RESPONSE COMPACTION SCHEME

SCAN TEST METHOD AND APPARATUS

Techniques For Scheduling Delivery Of Wireless Power In Wireless Po...

SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCU...

MULTI-STAGE TEST RESPONSE COMPACTORS

SCAN TESTING SYSTEM, METHOD AND APPARATUS

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD...