comprising an array of processing units with common control

Industry

CPC
G06F15/80

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

Current Industry

G06F15/80comprising an array of processing units with common control

Industries

Patents Grantslast 30 patents

Information Patent Grant
Reconfigurable dataflow unit with streaming write functionality
- Patent number 12,306,788
- Issue date May 20, 2025
- SambaNova Systems, Inc.
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual vector arithmetic logic unit
- Patent number 12,299,413
- Issue date May 13, 2025
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Message based processor with transmission disabling mode
- Patent number 12,298,933
- Issue date May 13, 2025
- Snap Inc.
- Orlando Miguel Pires dos Reis Moreira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore master/slave communications
- Patent number 12,299,768
- Issue date May 13, 2025
- Imagination Technologies Limited
- Michael John Livesley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load balancing system for the execution of applications on reconfig...
- Patent number 12,298,932
- Issue date May 13, 2025
- SambaNova Systems, Inc.
- Milad Sharif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 12,293,431
- Issue date May 6, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Artificial intelligence accelerator device
- Patent number 12,293,229
- Issue date May 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiaoyu Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Matrix multiplication hardware architecture
- Patent number 12,287,844
- Issue date Apr 29, 2025
- SHANGHAI INFINIGENCE AI INTELLIGENT TECHNOLOGY CO., LTD.
- Shulin Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for dividing work across accelerator devices
- Patent number 12,288,101
- Issue date Apr 29, 2025
- Intel Corporation
- Susanne M. Balle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General-purpose systolic array
- Patent number 12,287,756
- Issue date Apr 29, 2025
- Google LLC
- Reginald Clifford Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution unit sharing between processing cores in a cluster of a s...
- Patent number 12,282,447
- Issue date Apr 22, 2025
- QUALCOMM Incorporated
- Hithesh Hassan Lepaksha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing method based on a sorted operation unit graph for an iterat...
- Patent number 12,282,448
- Issue date Apr 22, 2025
- SambaNova Systems, Inc.
- Hong Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming constant extensions in the same execute packet in a VLIW pr...
- Patent number 12,265,827
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for offloading acceleration task scheduling operations...
- Patent number 12,260,257
- Issue date Mar 25, 2025
- Intel Corporation
- Susanne M. Balle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for performing multiplication of one or more ma...
- Patent number 12,260,248
- Issue date Mar 25, 2025
- Huawei Technologies Co., Ltd.
- Tal Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout-based data transfer between synchronized, interconnected pro...
- Patent number 12,260,253
- Issue date Mar 25, 2025
- SiMa Technologies, Inc.
- Gwangho Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Game engine on a chip
- Patent number 12,249,018
- Issue date Mar 11, 2025
- TMRW FOUNDATION IP S.ÀR.L.
- Cevat Yerli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible, scalable graph-processing accelerator
- Patent number 12,248,516
- Issue date Mar 11, 2025
- Advanced Micro Devices, Inc.
- Ganesh Dasika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic neural CPU processor
- Patent number 12,242,416
- Issue date Mar 4, 2025
- Northwestern University
- Jie Gu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core processor, multi-core processor processing method, and r...
- Patent number 12,242,415
- Issue date Mar 4, 2025
- Huawei Technologies Co., Ltd.
- Guozhu Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing apparatus with selectively delayed transmission of...
- Patent number 12,236,241
- Issue date Feb 25, 2025
- ARM Limited
- Xiaoyang Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable spatial array for matrix decomposition
- Patent number 12,235,793
- Issue date Feb 25, 2025
- Intel Corporation
- Long Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block data load with transpose into memory
- Patent number 12,229,570
- Issue date Feb 18, 2025
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor with non-blocking concurrent architecture
- Patent number 12,229,865
- Issue date Feb 18, 2025
- Imagination Technologies Limited
- Luke T Peterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for deep learning network execution pipeline...
- Patent number 12,229,569
- Issue date Feb 18, 2025
- Intel Corporation
- Liu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for synchronization of multi-thread lanes
- Patent number 12,223,353
- Issue date Feb 11, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250166114
- Publication date May 22, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION P...
- Publication number 20250165429
- Publication date May 22, 2025
- Micron Technology, Inc.
- Harold B Noyes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...
- Publication number 20250156186
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES
- Publication number 20250156222
- Publication date May 15, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING SYSTEM INCLUDING MULTI-CORE PROCESSOR AND OPERATING METHO...
- Publication number 20250147920
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Moongyung KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND COMPUTER-READABLE MEDIUM FOR PARALLELIZATION...
- Publication number 20250147921
- Publication date May 8, 2025
- CORNAMI, INC.
- Solomon Harsha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND CONTROL METHOD FOR PROCESSOR
- Publication number 20250147760
- Publication date May 8, 2025
- Preferred Networks, Inc.
- Tanvir AHMED
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Graphics Processor with Non-Blocking Concurrent Architecture
- Publication number 20250148688
- Publication date May 8, 2025
- Imagination Technologies Limited
- Luke T Peterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Spill-After Programming Model for the Streaming Wave Coalescer
- Publication number 20250130811
- Publication date Apr 24, 2025
- ADVANCED MICRO DEVICES, INC.
- Sean Keely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing an Edge of an Operation Unit Graph on a Reconfigurable Proc...
- Publication number 20250123995
- Publication date Apr 17, 2025
- SambaNova Systems, Inc.
- Hong SUH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quantum Controller with Modular and Dynamic Pulse Generation and Ro...
- Publication number 20250125793
- Publication date Apr 17, 2025
- Quantum Machines
- Yonatan Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20250117359
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
- Publication number 20250117360
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO
- Publication number 20250117271
- Publication date Apr 10, 2025
- HyperX Logic, Inc.
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE ARITHMETIC ENGINE CIRCUIT
- Publication number 20250117357
- Publication date Apr 10, 2025
- Cornami, Inc.
- Raymond J. Andraka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Heterogenous Acceleration of Workloads using xPUs and FPGAs
- Publication number 20250117358
- Publication date Apr 10, 2025
- Nicolas Tausanovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVOLUTION OPERATIONS WITH IN-MEMORY COMPUTING
- Publication number 20250117441
- Publication date Apr 10, 2025
- Rain Neuromorphics Inc.
- Nawab Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20250110737
- Publication date Apr 3, 2025
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleave Execution Circuit
- Publication number 20250103551
- Publication date Mar 27, 2025
- Apple Inc.
- Kanghong Yan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250104180
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS FOR TRANSPORTING OUTPUT VALUES OF NEURAL NETWORK LAYER
- Publication number 20250103341
- Publication date Mar 27, 2025
- AMAZON TECHNOLOGIES, INC.
- Kenneth Duong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTION UNIT SHARING BETWEEN PROCESSING CORES IN A CLUSTER OF A S...
- Publication number 20250103545
- Publication date Mar 27, 2025
- QUALCOMM Incorporated
- Hithesh Hassan LEPAKSHA
- G06 - COMPUTING CALCULATING COUNTING

comprising an array of processing units with common control

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Reconfigurable dataflow unit with streaming write functionality

Dual vector arithmetic logic unit

Message based processor with transmission disabling mode

Multicore master/slave communications

Load balancing system for the execution of applications on reconfig...

Sparse optimizations for a matrix accelerator architecture

Write merging on stores with different privilege levels

Artificial intelligence accelerator device

Matrix multiplication hardware architecture

Technologies for dividing work across accelerator devices

General-purpose systolic array

Execution unit sharing between processing cores in a cluster of a s...

Routing method based on a sorted operation unit graph for an iterat...

Hybrid victim cache and write miss buffer with fence operation

Forming constant extensions in the same execute packet in a VLIW pr...

Methods and apparatus for multi-banked victim cache with dual datapath

Technologies for offloading acceleration task scheduling operations...

Systems and methods for performing multiplication of one or more ma...

Layout-based data transfer between synchronized, interconnected pro...

Game engine on a chip

Flexible, scalable graph-processing accelerator

Systolic neural CPU processor

Data initialization techniques

Multi-core processor, multi-core processor processing method, and r...

Data processing apparatus with selectively delayed transmission of...

Programmable spatial array for matrix decomposition

Block data load with transpose into memory

Graphics processor with non-blocking concurrent architecture

Methods and apparatus for deep learning network execution pipeline...

Systems and methods for synchronization of multi-thread lanes

Patents Applicationslast 30 patents

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION P...

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES

DATA INITIALIZATION TECHNIQUES

COMPUTING SYSTEM INCLUDING MULTI-CORE PROCESSOR AND OPERATING METHO...

METHOD, APPARATUS, AND COMPUTER-READABLE MEDIUM FOR PARALLELIZATION...

PROCESSOR AND CONTROL METHOD FOR PROCESSOR

Graphics Processor with Non-Blocking Concurrent Architecture

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

Spill-After Programming Model for the Streaming Wave Coalescer

Routing an Edge of an Operation Unit Graph on a Reconfigurable Proc...

Quantum Controller with Modular and Dynamic Pulse Generation and Ro...

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO

RECONFIGURABLE ARITHMETIC ENGINE CIRCUIT

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

Heterogenous Acceleration of Workloads using xPUs and FPGAs

CONVOLUTION OPERATIONS WITH IN-MEMORY COMPUTING

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

Interleave Execution Circuit

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

CACHE STRUCTURE AND UTILIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

BUS FOR TRANSPORTING OUTPUT VALUES OF NEURAL NETWORK LAYER

EXECUTION UNIT SHARING BETWEEN PROCESSING CORES IN A CLUSTER OF A S...