Patent Application
20250173309
The present disclosure generally relates to a processor architecture with multiple dies, and more specifically to die-to-die dense packaging of deterministic streaming processors.
Over the last decade, data center operators have installed multicore processor systems in warehouse-scale computers. These systems have dozens to thousands of processing cores that vary widely in form and function, are used in powerful graphical processing units (GPUs), tensor processing units (TPUs), field programmable gate arrays (FPGAs), with many using data network controllers for efficient remote memory access. Such systems are often used for accelerating deep neural network training and inference (application of the trained neural network) performance for a wide range of uses in commerce, for example, convolutional neural networks (CNNs) for recommendation algorithms, computer vision and image classification for product searching; and recurrent neural networks (RNNs) for natural language processing in user interfaces. The heightened computational requirements of these models, many of which involve very large numbers of vector and matrix calculations, when used for millions of consumers and billions of transactions, have been the catalyst for a resurgence of architectural innovation.
In a conventional chip multiprocessor (CMP), processing cores are interconnected using an on-chip network to exchange data between all of the processing cores. In this simple load-store model, a set of general-purpose data registers are used as intermediate storage between the main memory systems and the processor cores, which can include arithmetic logic units (ALUs), that operate on data. Instructions are dispatched to each core and executed by the local integer or floating-point processing modules, while intermediate results are stored in the general-purpose registers. This load-store architecture moves data (also referred to as ‘operands’) and computed results between the registers and main memory. Instruction execution is often carried out over several stages: 1) instruction fetch, 2) instruction decode, 3) execution on ALUs, 4) memory read, and 5) memory write to update the results in the registers.
However, workloads for CMPs continue to grow both in size and complexity, presenting serious scalability, performance, and usability demands for traditional CMP architectures. Efficiently managing this demand requires abundant on-chip ALUs for the vector and matrix calculations, used at near-peak performance levels throughout program execution. Unfortunately, hardware complexity from added ALUs and other components substantially increased scheduling difficulties within many of these architectures. In turn, this impedes system performance as it is difficult to prevent runtime stalls. Furthermore, while architectural enhancements such as caches, branch predictors, and prefetchers help tremendously in improving performance, they do not bound worst-case performance.
Embodiments of the present disclosure are directed to an integrated circuit with one or more deterministic processors (e.g., tensor streaming processors (TSPs) or artificial intelligence processors) each having a functional slice architecture. In some embodiments, each deterministic processor is configured to process a machine learning model. Each deterministic processor is divided into a plurality of functional units organized into a plurality of functional slices. Each functional slice is configured to perform specific functions within the deterministic processor, which can include memory functional slices (MEMs) for storing operand data, arithmetic functional slices for performing operations on received operand data (e.g., vector processing, matrix manipulation), and/or the like. Functional units of the deterministic processor are configured to stream operand data across a first (e.g., temporal) dimension in a direction indicated in a corresponding instruction, and receive instructions across a second (e.g., spatial) dimension. The compiler for the deterministic processor is aware of the hardware configuration of the processor, and configures the timing of data and instruction flows such that corresponding data and instructions are intersected at each computational element at a predetermined time. Each functional slice of the deterministic processor can operate on a set of data lanes in a Single Instruction Multiple Data (SIMD) manner. The set of data lanes can be referred to herein as a “superlane” and represents a cross-section of all the functional slices on a processor chip.
Embodiments of the present disclosure are directed to an integrated circuit. The integrated circuit includes a first die and a second die connected to the first die forming a tile structure. The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension. The tile structure is configured to operate as a single core processor for model-parallelism across the first die and the second die of the tile structure.
Embodiments of the present disclosure are further directed to an integrated circuit that comprises an array of tile structures. Each tile structure in the array includes a first die, and a second die connected to the first die in a face-to-face (F2F) configuration. The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension forming an offset alignment between the first die and the second die. In some configurations, the first shift amount may be up to 50% of a first size of the first die (or the second die) along the first dimension, and/or the second shift amount may be up to 50% of a second size of the first die (or the second die) along the first dimension. The array of tile structures is configured to operate as a single core processor for model-parallelism across the tile structures.
Embodiments of the present disclosure are further directed to an integrated circuit comprising stacked tile structures. The integrated circuit includes a first plurality of tile structures coupled to a first side of a tile-to-tile (T2T) bridge, and a second plurality of tile structures coupled to a second side of the T2T bridge opposite the first side. Each tile structure in the first and second pluralities includes a first die and a second die connected in a F2F configuration. The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension. The integrated circuit further includes a first stack of high bandwidth memories (HBMs) coupled to the first side, a second stack of HBMs coupled to the second side, and a heat sink coupled to outer surfaces of the first plurality of tile structures and the first stack of HBMs. In some embodiments, the integrated circuit includes a cuboid structure of tile structures. The tile structures of the cuboid structure are configured to operate as a single core processor for model-parallelism across the tile structures.
Embodiments of the present disclosure further relate to a process (or method) of computing using one or more deterministic streaming processor (e.g., tensor streaming processor) of an integrated circuit. The process includes: initiating issuance of instructions for execution by processing units (e.g., computational elements of one or more functional slices) across a plurality of dies of one or more tile structures of the integrated circuit, initiating streaming of data through the processing units across the plurality of dies of the one or more tile structures for execution of the instructions, and returning of resulting data to one or more memory slices of the one or more tile structures.
Embodiments of the present disclosure further relate to a non-transitory computer-readable storage medium comprising stored thereon computer executable instructions, which when executed by a compiler operating on at least one computer processor cause the at least one computer processor to: initiate issuance of instructions for execution by processing units (e.g., computational elements of one or more functional slices) across a plurality of dies of one or more tile structures of the integrated circuit, initiate streaming of data through the processing units across the plurality of dies of the one or more tile structures for execution of the instructions, and initiate returning of resulting data to one or more memory slices of the one or more tile structures.
Embodiments of the present disclosure further relate to an integrated circuit implemented as a die-to-die (D2D) dense packaging of deterministic streaming processors (e.g., tensor streaming processors). The integrated circuit includes multiple dies connected in a D2D configuration, and each die includes a respective deterministic streaming processor. The integrated circuit can include a first die and a second die connected to the first die via a D2D interface circuit in the D2D configuration forming a D2D structure with the first die. The D2D interface can connect a first plurality of superlanes (i.e., groups of first streaming data lanes) of the first die with a second plurality of superlanes (i.e., groups of second streaming data lanes) of the second die for streaming data between the first die and the second die along a first direction or a second direction orthogonal to the first direction. The D2D structure is configured to function as a single core processor for model-parallelism across the first and second dies of the D2D structure.
Embodiments of the present disclosure further relate to a process (or method) of computing using one or more deterministic streaming processors (e.g., tensor streaming processors) of an integrated circuit. The process (e.g., performed by a compiler) includes: initiating issuance of a plurality instructions for execution by a plurality of processing units (e.g., computational elements of one or more functional slices) across a first die and a second die, the second die connected to the first die via a D2D interface circuit in a D2D configuration forming a D2D structure with the first die; and initiating streaming of data between a first plurality of superlanes of the first die and a second plurality of superlanes of the second die via the D2D interface circuit along a first direction or a second direction orthogonal to the first direction for execution of the plurality of instructions.
Embodiments of the present disclosure further relate to a non-transitory computer-readable storage medium comprising stored thereon computer executable instructions, which when executed by a compiler operating on at least one computer processor cause the at least one computer processor to: initiate issuance of a plurality of instructions for execution by a plurality of processing units (e.g., computational elements of one or more functional slices) across a first die and a second die, the second die connected to the first die via a D2D interface circuit in a D2D configuration forming a D2D structure with the first die; and initiate streaming of data between a first plurality of superlanes of the first die and a second plurality of superlanes of the second die via the D2D interface circuit along a first direction or a second direction orthogonal to the first direction for execution of the plurality of instructions.
Figure (
The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles, or benefits touted, of the disclosure described herein.
The Figures (FIGS.) and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed.
Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the disclosed system (or method) for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.
Disclosed are configurations that include an integrated circuit with one or more deterministic processors (e.g., tensor streaming processors (TSPs) or artificial intelligence processors). Each deterministic processor can have a functional slice architecture. In some embodiments, each deterministic processor is configured to process a machine learning model. Each deterministic processor is divided into a plurality of functional units. The functional units are organized into a plurality of functional slices. Each functional slice is configured to perform specific functions within the deterministic processor. The deterministic processor can include memory functional slices (MEMs) for storing operand data, arithmetic functional slices for performing operations on received operand data (e.g., vector processing, matrix manipulation), and/or the like. Functional units of the deterministic processor are configured to stream operand data across a first (e.g., temporal) dimension in a direction indicated in a corresponding instruction, and receive instructions across a second (e.g., spatial) dimension. The compiler for the deterministic processor is aware of the hardware configuration of the processor, and configures the timing of data and instruction flows such that corresponding data and instructions are intersected at each computational element at a predetermined time. Each functional slice of the deterministic processor can operate on a set of data lanes in a Single Instruction Multiple Data (SIMD) manner. The set of data lanes can be referred to herein as a “superlane” and represents a cross-section of all the functional slices on a processor chip.
The disclosed embodiments are directed to a deterministic streaming processor having a functional slicing architecture. In some embodiments, the deterministic streaming processor can comprise a tensor streaming processor (TSP) having a functional slicing architecture, which can be used for hardware-accelerated machine learning (ML) applications.
The deterministic streaming processor (e.g., TSP) comprises a plurality of “computational elements,” each computational element corresponding to a functional unit within the processor. The on-chip memory and network-on-chip (NoC) of the processor architecture are fused to provide both storage of operands and results, and can act as a conduit for transferring operand and/or result data to/from the functional units of the processor. The computational elements of the deterministic streaming processor are divided between different functionalities (e.g., memory, arithmetic operation, etc.), and are organized as functional slices which operate on multi-dimensional data (e.g., tensors). For example, each functional slice is composed from computational elements which border (or abut) each other, both horizontal and vertically, to form the functional slice. The number of computational elements and computation granularity of each computational element can be selected to take advantage of the underlying technology on which it is built. Taken together, the number of computational elements (N) and the word granularity (M) of a memory (e.g., static random-access memory (SRAM)) yields the vector length (VL) of the machine.
In some embodiments, each functional slice of the deterministic streaming processor functions independently, and receives instructions from an instruction control unit (ICU). The ICU can pass instructions to a first computational element of the functional slice, which are then propagated in a first temporal dimension of the processor along the functional slice to the remaining computational elements of the functional slice. On the other hand, data operands for storage and/or processing can be passed between different functional slices of the deterministic streaming processor, in a second spatial dimension of the processor perpendicular to the first temporal dimension. As such, the data flow and the instruction flow of the deterministic streaming processor are separated from each other.
In some embodiments, a compiler for the deterministic streaming processor is aware of the hardware configuration of the deterministic streaming processor, and synchronizes the timing of data and instruction flows such that corresponding data and instructions are received at each computational element with a predetermined temporal relationship (e.g., during the same clock cycle, separated by a predetermined delay, etc.). In some embodiments, the predetermined temporal relationship can be based upon the hardware of the deterministic streaming processor, a type of instruction, and/or the like. Because the temporal relationship between data and instructions are known by the compiler, the operand data received by a computational element does not include any metadata indicating what the data is to be used for. Instead, each computational element receives instructions, and based upon the predetermined timing, performs the instruction on the corresponding data. This allows for the data and instructions to flow through the deterministic streaming processor more efficiently.
Embodiments of the present disclosure are directed to an integrated circuit. The integrated circuit includes a first die and a second die connected to the first die forming a tile structure. The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension. The tile structure is configured to operate as a single core processor for model-parallelism across the first and second dies of the tile structure.
Embodiments of the present disclosure are further directed to an integrated circuit that comprises an array of tile structures. Each tile structure in the array includes a first die, and a second die connected to the first die in a face-to-face (F2F) configuration. The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension forming an offset alignment between the first die and the second die. The array of tile structures is configured to operate as a single core processor for model-parallelism across the tile structures.
Embodiments of the present disclosure are further directed to an integrated circuit comprising stacked tile structures. The integrated circuit includes a first plurality of tile structures coupled to a first side of a tile-to-tile (T2T) bridge, and a second plurality of tile structures coupled to a second side of the T2T bridge opposite the first side. Each tile structure in the first and second pluralities includes a first die and a second die connected in a F2F configuration. The first die is shifted relative to the second die by a first shift amount along a first dimension and by a second shift amount along a second dimension orthogonal to the first dimension. The integrated circuit further includes a first stack of high bandwidth memories (HBMs) coupled to the first side, a second stack of HBMs coupled to the second side, and a heat sink coupled to outer surfaces of the first plurality of tile structures and the first stack of HBMs. The stacked tile structures (e.g., stacked in a cuboid structure) is configured to operate as a single core processor for model-parallelism across the tile structures.
In accordance with embodiments of the present disclosure, the processor plane comprises a TSP, e.g., as can be commercially available from GROQ, INC. of Mountain View, California. It is to be understood that although many embodiments described herein use a TSP as the preferred processors, other deterministic processors can be used in commercial applications. Figure (
Certain core architectural elements set the TSP apart from GPU and accelerators. In a conventional chip multiprocessor (CMP), each “computational element” is an independent core that is interconnected using the on-chip network to exchange data between cores. Instruction execution is carried out over several stages: (i) instruction fetch (IF), (ii) instruction decode (ID), (iii) execution (EX) on Arithmetic Logic Units (ALUs), (iv) memory access (MEM), and (v) writeback (WB) to update the results in the general-purpose registers (GPRs).
In contrast from conventional multicore, where each computational element is a heterogeneous collection of functional units but globally homogeneous, the TSP inverts that to have a local functional homogeneity but chip-wide (global) heterogeneity. More specifically, the TSP reorganizes the homogeneous two-dimensional mesh of cores into the functionally sliced microarchitecture shown in
In this organization, each functional slice is independently controlled by a sequence of instructions specific to its on-chip role. For instance, the MEM functional slices support Read and Write but not, necessarily Add or Mul, which are typically performed in arithmetic functional slices (e.g., the vector execution module (VXM) and matrix execution module (MXM) functional slices) for some typical machine learning (ML) algorithms, such as the linear regression algorithm.
All functional slice's computational elements execute the same instruction stream—Single Instruction Multiple Data (SIMD) instructions. Thus, the common instruction decode and dispatch logic can be factored out into its own computational element (e.g., ICU) and decompose the normal instruction execution pipeline into two areas: (i) instruction fetch, decode, and parceling and (ii) operand read, execute, and writeback. This approach decouples the memory subsystem from the functional units retrieving their operands and depositing results.
In some embodiments, each functional slice implements, e.g., a 20-stage vector pipeline that spans the computational elements of each functional slice, with each computational element producing 16 elements of the 320-element maximum vector length. This organization naturally decomposes instruction flow in the vertical dimension, and data flow in the horizontal dimension as the data flow passes over different function types. With this processor organization, instruction execution is carried out by different computational elements: instruction fetching and decoding in the ICU and operand decode, execution and writeback at each computational element of the functional slice as the (vertical flowing) dispatched instruction intersects with the (horizontal flowing) operand data on which the dispatched instruction is operating. It will be appreciated that reference to ‘vertical’ and ‘horizontal’ or ‘north’, ‘south’, ‘east’ and ‘west’ are used in connection with the illustrations shown in the Figures, are abstractions that are solely intended to aid the reader and should not be inferred as technical limitations.
It is noted that the “east-west-north-south” directionality is provided herein for ease of discussion and relativity. Furthermore, the “east-west-north-south” directionality is used as a reference for explanation of processing flow as described herein and is not intended to be limited with respect to a label of a particular direction. For example, north-south could be reoriented to east-west and the principles currently described with east-west could apply to the reoriented north-south. In another example of the directionality not intended to be limited to the description per the reference noted, directionality could be referenced such that north-south is up-down and east west is right-left and the principles would accordingly apply.
In one embodiment, 320 lanes are overlaid on the TSP 100 where each computational element in the on-chip mesh operates on, e.g., 16-lanes in a SIMD manner. The 16-lane unit can be referred to herein as a “superlane” and represents a cross-section of all the functional slices on the chip. As such, a superlane can represent the architecture's minimum vector length (minVL) of, e.g., 16 elements. Likewise, the vertical composition of 20 tiles forming a functional slice can produce a maximum vector length (maxVL) of, e.g., 20×16=320 functional units. Each of the 144 independent on-chip ICUs can issue one or more instructions per clock cycle. The compiler has explicit control of a program order in each instruction queue, e.g., by generating an assembled program 140 for execution by the ICUs and functional slices. There are 64 logical streams per lane for moving operands or results on-chip with, e.g., 32 streams eastward and 32 streams westward. The 220 MB of globally shared SRAM can deliver 32 bytes per lane of stream bandwidth and low-latency access to model parameters. For example, MEM can read and M×M can install more than e.g., 100,000 weights into a 320×320 array (i.e., 320 lanes×320 functional units) in less than 30 clock cycles including SRAM and on-chip network transit delays.
As shown in
The MEM 111/112 and the SXM 113/114 provide deterministic routing of stream data as the stream data flows in the X and Y dimensions, respectively. With the TSP architecture 100, functional slices interact with streams of data in a producer-consumer fashion. That is, the functional slices consume operands from streams and produce results onto a (possibly different) stream, like an assembly line operator (functional slice) and conveyor belt (stream).
Conceptually, the functional slices are fixed and data is flowing across computational elements as shown in
Streams provide a programming abstraction and are a conduit through which data flows between functional slices. Unlike GPRs, the functional slices operate on streams of parallel data flowing east or west (horizontally) across the chip. The horizontally flowing streams carrying operands intercept the vertically (northward) flowing instructions (see
Streams are implemented in hardware by a chip-wide streaming register file. Streams are architecturally visible and transport operands and results between functional slices. A common software pattern involves reading operand data from one or more MEM functional slices that is then subsequently consumed and operated on by a downstream arithmetic functional slice. The results of the operation are then produced onto another stream such that they can be written back to memory or passed to subsequent computational elements. For example, a Z=X+Y operation might require four instructions: Read S1, X and Read S2, Y are executed on two MEM functional slices and directed inward toward an ALU functional slice to perform the Add S1, S2, S3. Lastly, the result is stored back to memory via a Write S3, Z. The streams represent a collection of N-elements, operated upon in a SIMD manner by each functional slice.
By way of example, a TSP architecture makes several deliberate tradeoffs on the hardware-software interface, pushing the complexities associated with scheduling into the compiler. Specifically, it falls on the compiler to precisely schedule instructions to use the hardware correctly and efficiently. At times this can involve selecting one of several means by which an algorithm or meta-operation can be realized on the hardware. Removing the control complexity of dynamic instruction scheduling for multi-issue execution units allows the ICU to be relatively small, accounting for, e.g., less than 3% of the chip area.
The compiler has access to, e.g., 320-lane programming abstraction overlaid on a TSP architecture where each computational element in the on-chip mesh operates on 16-lanes in a SIMD manner. The 16-lane unit can be referred to as a “superlane” which is a cross-section of all the functional slices on the chip and the minimum granularity of computation. As such, a superlane represents the architecture's minimum vector length, minVL, of 16 elements. Likewise, the vertical composition of 20 tiles to form a functional slice produces a maximum vector length, max VL, of 20×16=320 elements.
The compiler has access to, e.g., 144 independent instruction queues (i.e., ICUs) on-chip: (a) six for westward MXM including two independent two-dimensional MAC (multiply-accumulate) arrays; (b) 14 for westward SXM for intra-superlane and inter-lane switching by rearranging elements of vectors; (c) 44 for westward MEM including 44 parallel functional slices of static random-access memory (SRAM); (d) 16 for VXM including 16 vector ALUs per lane; (e) 44 for eastward MEM-including 44 parallel functional slices of SRAM; (f) 14 for eastward SXM; and (g) six for eastward MXM including two independent two-dimensional MAC arrays, whereas each instruction queue can issue one or more instructions per cycle and the compiler has explicit control of the program order in each instruction queue.
The compiler has access to, e.g., 64 logical streams per lane. For example, 32 logical streams are required to operate on 16 minVL per lane for moving operands or results on-chip with 32 streams eastward, and 32 streams westward.
The compiler has access to, e.g., 220 MBytes of globally shared SRAM that delivers 32 bytes per lane of stream bandwidth and low-latency access to model parameters. For example, MEM can read and M×M can install 400K weights into all four 320×320 arrays in less than 40 operational cycles including SRAM and on-chip network transit delay.
Streams are designated by both an identifier (0, . . . ,31) and direction. For example, in (28) designates stream 28 inward, and out (24) designates stream 24 toward the outward edge of the chip. The direction of a stream can be designated as inward (toward the chip bisection) or outward (toward the outward edge of the chip), or the direction can be designated as eastward or westward, as shown in
The components of a superlane are organized spatially as shown in
The first functional area (i.e., ICU) provides explicit instruction fetching with IFetch instruction(s), and inter-slice synchronization using Sync and Notify instructions to perform chip-wide barrier synchronization among participating functional slices. A repeated-NOP (no-op) instruction allows for precise cycle-by-cycle control of inter-instruction delay. For example, the compiler has cycle-accurate control when scheduling two operations A and B using an intervening NOP so that N cycles separate them, e.g., OpA NOP(N) OpB.
The second functional area (i.e., VXM) consists of a 4×4 mesh of ALUs in each lane for point-wise arithmetic operations.
The third functional area (i.e., MXM) consists of four independent two-dimensional MAC arrays that operate on, e.g., INT8 or FP16 data types.
On-chip data movement uses the fourth functional area (i.e., SXM) for intra-superlane and inter-lane switching by rearranging elements of vectors. The SXM is analogous to the NET interface to communicate between cores in
The fifth functional area (i.e., the east and west hemisphere of on-chip MEM module) is composed of 44 parallel MEM functional slices of SRAM and provides the memory access concurrency necessary to fully utilize the 32 streams in each East or West direction. Each functional slice provides 13-bits of physical addressing of 16-byte memory words, each byte maps to a lane, for a total of 220 MBytes of on-chip SRAM.
An additional sixth functional area includes C2C modules configured to provide Send and Receive primitives for exchanging 320-byte vectors between a pair of TSP chips. One possible TSP implementation has, e.g., a total of 16×4 links operating at 30 Gbps each for a total off-chip bandwidth of 16×4×30 Gbps×2 directions=3.84 Tb/s (Tera-bytes per second) of off-chip pin bandwidth that can be flexibly partitioned to support high-radix interconnection networks of TSPs for large-scale systems. The host interface for peripheral component interconnect express (PCIe) Gen4 can be also handled in this module. The host interface provides a lightweight direct memory access (DMA) engine to emplace a model onto the TSP memory and provides an entry point for bootstrapping the model execution. The host interface also provides a general mechanism for passing interrupts to the host, which can be necessary in the event a multi-bit memory error is observed, for example.
Table I provides a summary of example instructions for each functional slice, in accordance with some embodiments.
outputs
A sequence of instructions performed on different functional slices can be chained to create more complex actions without the need to write back intermediate results to memory. This allows efficient processing of streams at full bandwidth and lowest latency.
Machine learning algorithms typically operate on vectors with coefficients of a specified data type (e.g., INT8, FP16, etc.). These vectors can be interpreted as an abstraction over the underlying data, whose elements can be processed by the same operation in a SIMD manner. The TSP operates on vectors, sometimes organized into rank-2 tensors, and relies on the graph-lowering compiler to transform higher rank tensors into rank-2 tensors.
The TSP's programming model is a producer-consumer model where each functional slice acts as a consumer and a producer of one or more streams. When a vector is read from a main memory, the vector is given a stream identifier (0, . . . , 31) and direction: eastward, or westward. Once the vector is read into a stream register it is a stream and is “flowing” in the given direction in the following sense: given spatially adjacent functional slices at coordinates x0, x1, x2 (where the spatial coordinate increases in the direction of flow), then at a given time t1, the vector representing stream s1 at functional slice x1 can be accessed as operands by that functional slice. Similarly, the functional slices at x0 and x2 will have access to different stream values for the same stream register. In the following cycle ti+1, the value s1 either propagated to the functional slice at x2, or else the value s1 is overwritten with a result r1 produced by the functional slice at x1 at cycle t. Similarly, the stream value so that was present to be consumed by the functional slice at coordinate x0 at time ti will be (absent x0 overwriting the value at time ti) available in the next cycle ti+1 to the functional slice at x1. Stream operands are steered toward the functional slice that is consuming them and producing a result stream. Streams are constantly flowing across the chip, serving as how functional slices communicate with one another.
In the TSP programming model, an instruction is issued on a functional slice at a given compiler-scheduled time t and executes as a SIMD operation on stream-supplied operand vectors (e.g., of up to 320-elements), producing vectors of the same length on result streams. For example, at the micro-architectural level, the 320-element SIMD instruction is pipelined across the vertical stack of computational elements in the functional slice. That is, at the scheduled time t, the instruction would be issued to the bottom-most computational element of the functional slice, e.g., corresponding to the first 16-element superlane of operand/result vectors. In the subsequent operational cycle, the instruction would be propagated to the next computational element northward in the functional slice, which in turn executes the instruction on the next 16-element super lane of operand vectors. This process continues cycle-by-cycle until the process has traversed, e.g., all 20 computational elements in the functional slice. The combination of vertical instruction pipelining described above, along with the need for operands and instructions to coincide at a precise time, results in a spatial “stagger” of SIMD operand and result data.
Embodiments of the present disclosure relate to tile structures for implementation of multiple die devices. A tile structure can include a first array of processing units on a first die that is connected in a face-to-face (F2F) configuration with a second die having a second array of processing units. The tile structure can further include specific interfaces that allow connection with one or more other tile structures (i.e., other die) for implementing various multiple die devices having either multiple processors or, in some embodiments, a multiple-die single processor such as the TSP commercially available from GROQ, INC. The tile structure presented herein allows for efficient coupling of multiple tiles without utilizing any interposer based interface, e.g., silicon-based interposer. In some other embodiments, a tile structure presented herein comprises a pair of artificial intelligence (AI) processors connected in the F2F configuration, a Face-to-Back (F2B) configuration or a Back-to-Back (B2B) configuration.
The die 202 (i.e., with a portion of the die 202 forming the ledge) can be shifted relative to the die 204 (i.e., with a portion of the die 204 forming the shelf) by a first shift amount along a first dimension (e.g., x dimension or horizontal dimension) and by a second shift amount along a second dimension (e.g., y dimension or vertical dimension) orthogonal to the first dimension. The first shift amount can be equal to or different than the second shift amount. The die 202 can comprise a first TSP having a first plurality of functional units (i.e., functional slices), and the die 204 can comprise one of: a second TSP having a second plurality of functional units (i.e., functional slices), a memory device (e.g., HBM), an interface chip, some other chip, or some combination thereof. In a preferred embodiment, the tile structure 200 forms a single streaming processor (i.e., a single core TSP) with processing units (i.e., functional slices) on each die 202, 204. In other embodiments, the tile structure 200 can comprise a plurality of multiple core devices or other circuits. The tile structure 200 and ledge/shelf configuration shown in
The interface circuitry of the die 202 can include a first set of die-to-die (D2D) pins 208, a second set of D2D pins 210, a first set of tile-to-tile (T2T) pins 212, and a second set of T2T pins 214. A first D2D interconnect area comprising the first set of D2D pins 208 and a second D2D interconnect area comprising the second set of D2D pins 210 represent interface areas of the die 202 for connection with the die 204 in the F2F configuration (as further shown in
A ledge zone of the die 202 (and similarly a shelf zone of the die 204) can include the first and second sets of T2T pins 212, 214 used for connecting the tile structure 200 with one or more other tile structures. Areas around the T2T pins 212, 214 can form the ledge zone (or similarly the shelf zone for the die 204 of the same structure as the die 202) to enable the tile stricture 200 and another tile structure to mutually interconnect forming an electrical connection wherever their corresponding T2T pins align. The T2T pins 212, 214 can be sufficiently spaced away to align with corresponding T2T pins of an adjacent tile structure and any required die-to-die separation (e.g., in the order of 0.1 mm to 0.5 mm). The ledge zone of the die 202 (and similarly the shelf zone of the die 204) is bifurcated into two areas such that one area is along a ‘side’ edge of the die 202 and the other area is along a ‘top’ edge of the die 202 (or ‘bottom’ edge of the die 204). Thus, the tile structure 200 can couple to a pair of tile structures using the two ledge areas of the die 202 to form a closely coupled three-structure device. Similarly, the die 204 of the tile structure 200 can couple to another pair of tile structures using corresponding T2T pins in the shelf areas of the die 204.
In some embodiments, the T2T bridge 225 is employed for delivering a power from one die of the tile structure 220 for another die of the adjacent tile structure. In such cases, the mirror imaging can be required between the ledge and shelf dies of the tile structure 220, e.g., for implementation of power supply VDD and VSS connections. The T2T pins 230 of the T2T bridge 225 are preferably positioned in a zone proximate to edges of a T2T bridge die. For example, an area along an edge of the T2T bridge die can contain a first subset of the T2T pins 230 and an area along either the top or the bottom of the T2T bridge die can contain a second subset of the T2T pins 230. The T2T pins 230 when connected to pins of another tile structure or die can form an electrical connection that enable high speed data transmission because of the low ohmic connection formed thereby.
In one or more embodiments, as further shown in
It should be noted that closely positioning dies of adjacent tile structures can provide improved thermal conductivity for removal of heat from top (and/or bottom) sides of the connected tile structures. The F2F tile configuration presented herein represents a preferred approach to ensure virtually no gap between dies of adjacent tile structures. Having good and uniform thermal conduction facilitates efficient cooling and removal of heat using, e.g., a cooling system at the top side of the tile structure. More details about the cooling of the tile structures is provided below in conjunction with
In some embodiments, at least a subset of T2T pins of the die 255 (and/or the die 260) includes one or more through-silicon via (TSV) connectors 265. The TSV connectors 265 can allow the tile structure 250 to be connected vertically (e.g., along z dimension) with another tile structure in a F2F configuration, F2B configuration or B2B configuration (e.g., in addition to horizontal connections shown in
In some embodiments, as shown in
As shown in
Each die 505A and 505B in the tile structure 500 can include a TSP having an array of computational elements (e.g., as part of functional/memory slices) on a substrate. Alternatively, instead of a TSP, one of the dies 505A, 505B can comprise a memory device (e.g., HBM), an interface device (e.g., a bridge die), or some other device. A plurality of D2D pins 510A, 510B can be positioned on each die 505A, 505B. It can be observed that each die 505A, 505B can be divided into four quadrants, and each quadrant in each die 505A, 505B can include a portion of D2D pins 510A, 510B for a direct high speed connection with a corresponding pair of D2D pins 510A, 510B in the adjacent die. As shown in
Direct connection of a pair of dies 505A, 505B illustrated in
Each die 605A and 605B in the tile structure 600 can include a TSP having an array of computational elements (e.g., as part of functional/memory slices) on a substrate. Alternatively, instead of a TSP, one of the dies 605A, 605B can comprise a memory device (e.g., HBM), an interface device (e.g., a bridge die), or some other device. A plurality of D2D pins 610A, 610B can be positioned on each die 605A, 605B. Similarly, as in the case of tile structure 500 in
Referring back to
The tile structure 600 in
Each tile structure 710A through 710H can have the same configuration as the tile structure 200. Thus, each tile structure 710A through 710H can comprise a first die and a second die connected to the first die in the F2F configuration. The first die can be shifted relative to the second die by a first shift amount along the first dimension and by a second shift amount along the second dimension forming an offset alignment between the first die and the second die. The first die in each tile structure 710A through 710H can comprise a TSP, and the second die in each tile structure 710A through 710H can comprise another TSP, a memory device (e.g., HBM device), an interface device, some other device, or some combination thereof.
A top view 705A of the integrated circuit 700 illustrates the tile structures 710A, 710B, 710C, 710D mutually connected via a first side (e.g., top side) of the T2T bridge 715. Similarly, a bottom view 705B of the integrated circuit 700 illustrates the tile structures 710E, 710F, 710G, 710H mutually connected via a second side (e.g., bottom side) of the T2T bridge 715 opposite the first side. The T2T bridge is implemented as a bridge die with T2T pins (e.g., interconnection pads) on both sides of the bridge die. At least a subset of the T2T pins on the first side of the T2T bridge 715 aligns with corresponding T2T pins of the tile structures 710A, 710B, 710C, 710D. Similarly, at least a subset of the T2T pins on the second side of the T2T bridge 715 aligns with corresponding T2T pins of the tile structures 710E, 710F, 710G, 710H. Thus, the integrated circuit 700 effectively includes two horizontal layers of tile structures—a first horizontal layer of tile structures 710A, 710B, 710C, 710D and a second horizontal layer of tile structures 710E, 710F, 710G, 710H interconnected along a vertical dimension (e.g., z dimension) via the T2T bridge 715.
Each tile structure TS1 through TS32 can have the same configuration as the tile structure 200. Thus, each tile structure TS1 through TS32 can comprise a first die and a second die connected to the first die in the F2F configuration. The first die can be shifted relative to the second die by a first shift amount along the first dimension and by a second shift amount along the second dimension forming an offset alignment between the first die and the second die. The first die in each tile structure TS1 through TS32 can comprise a TSP, and the second die in each tile structure TS1 through TS32 can comprise another TSP, a memory device (e.g., HBM device), an interface device, some other device, or some combination thereof.
A top view 725A of the integrated circuit 720 illustrates the tile structures TS1 through TS16 mutually connected via a first side (e.g., top side) of the T2T bridge 730. Similarly, a bottom view 725B of the integrated circuit 720 illustrates the tile structures TS17 through TS32 mutually connected via a second side (e.g., bottom side) of the T2T bridge 730 opposite the first side. The T2T bridge 730 is implemented as a bridge die with T2T pins (e.g., T2T interconnection pads) on both sides of the bridge die. At least a subset of the T2T pins on the first side of the T2T bridge 730 aligns with corresponding T2T pins of the tile structures TS1 through TS16. Similarly, at least a subset of the T2T pins on the second side of the T2T bridge 730 aligns with corresponding T2T pins of the tile structures TS17 through TS32. Thus, the integrated circuit 720 effectively includes two horizontal layers of tile structures—a first horizontal layer of tile structures TS1 through TS16 and a second horizontal layer of tile structures TS17 through TS32 interconnected along a vertical dimension (e.g., z dimension) via the T2T bridge 730.
Each tile structure in the integrated circuit 800 can have the same configuration as the tile structure 200. A first die in each tile structure of the integrated circuit 800 can comprise a TSP, and a second die in each tile structure of the integrated circuit 800 can comprise another TSP, a memory device (e.g., HBM device), an interface device, some other device, or some combination thereof. A number of tile structures connected via the top side of the T2T bridge 810 is 4N, a number of tile structures connected via the bottom side of the T2T bridge 810 is 4N, and N is an integer. Thus, the total number of tile structures in the integrated circuit 800 can be 8N (e.g., N=1, 2, 3, or 4).
The integrated circuit 800 further includes a first stack 815A of memory devices (e.g., stack of HBM devices) placed on the first side of the T2T bridge 810, e.g., spatially between the tile structure 805A and the tile structure 805B. The HBM stack 815A can comprise one or more HBMs stacked on top of each other in the F2B configuration or in the B2B configuration (e.g., via TSV connectors). The integrated circuit 800 further includes a second stack 815B of memory devices (e.g., stack of HBM devices) placed on the second side of the T2T bridge 810, e.g., spatially between the tile structure 805C and the tile structure 805D. The HBM stack 815B can comprise one or more HBMs stacked on top of each other in the F2B configuration or in the B2B configuration (e.g., via TSV connectors). The tile structures in the integrated circuit 800 along with the HBM stacks 815A, 815B can function as a single core processor for model-parallelism across a plurality of dies of the tile structures and HBMs.
The integrated circuit 820 further includes a first stack 835A of memory devices (e.g., stack of HBM devices) placed on the first side of the T2T bridge 830, e.g., spatially between the tile structure 825A and the tile structure 825B. The HBM stack 835A can comprise one or more HBMs stacked on top of each other in the F2B configuration or in the B2B configuration (e.g., via TSV connectors). The integrated circuit 820 further includes a second stack 835B of memory devices (e.g., stack of HBM devices) placed on the second side of the T2T bridge 830, e.g., spatially between the tile structure 825C and the tile structure 825D. The HBM stack 835B can comprise one or more HBMs stacked on top of each other in the F2B configuration or in the B2B configuration (e.g., via TSV connectors). The tile structures in the integrated circuit 820 along with the HBM stacks 835A, 835B can function as a single core processor for model-parallelism across a plurality of dies of the tile structures and HBMs.
The integrated circuit 820 further includes a heat sink 840 coupled to outer surfaces of the tile structures 825A, 825B (and any additional tile structures coupled to the first side of the T2T bridge 830) and the HBM stack 835A. The heat sink 840 can be configured to dissipate heat from the tile structures 825A through 825D (and any additional tile structures coupled to the first and second sides of the T2T bridge 830) and the HBM stacks 835A, 835B. In one or more embodiments, the heat sink 840 is implemented as a heat sink die comprising, e.g., a metal layer formed on top of a substrate. In one or more other embodiments, the heat sink 840 can be implemented as a thermal filler filling gaps between tile structures. For example, a thermal filler of the heat sink 840 can fill gaps between the tile structure 825A and the tile structure 825B (and any additional tile structures coupled to the first side of the T2T bridge 830). A thermal filler of the heat sink 840 can be, e.g., silicon (graphene based) filler or graphene tube placed on a copper cold plate in contact with silicon.
The integrated circuit 820 can further include a power supply layer 845, e.g., coupled to outer surfaces of the tile structures 825C, 825D (and any additional tile structures coupled to the second side of the T2T bridge 830) and the HBM stack 835B. The power supply layer 845 can include an array of C4 bumps to provide power supply networks for lower layers of silicon in the integrated circuit 820 (e.g., lower dies of HBM stack 835B, lower dies of the tile structures 825C, 825D and any additional tile structures coupled to the second side of the T2T bridge 830). Other dies (i.e., upper layers of silicon) in the integrated circuit 820 can include power delivery via TSV connectors.
As shown in
The cuboid structure 900 can further include a plurality of heatsinks (not shown in
In some embodiments, a compiler controlling data operations performed on dies of the cuboid structure 900 can be configured to provide a specific silicon-to-power tradeoff, e.g., by running twice the number of dies of the cuboid structure 900 at 50% of a maximum defined clock rate. Additionally, or alternatively, the compiler can map utilization to resources within the cuboid structure 900 to stagger heat generation and optimize local heating of dies and tile structures. In one or more embodiments, each dies of the tile structures in the cuboid structure 900 can be of a different size and/or perform different functions. The per-die granularity of size and functionality of the cuboid structure 900 can be exploited by the compiler for optimizing silicon-to-power tradeoff at the cuboid structure 900.
In some embodiments, one or more cuboid structures 900 are housed in a rack and can be employed in a data center. The data center can contain thousands of such racks. Each cuboid structure 900 in the rack can be configured to operate as a single core deterministic streaming processor (e.g., a TSP) that runs a corresponding model (e.g., a machine learning model). Thus, multiple models can be executed asynchronously across the multiple cuboid structures 900 in the rack. The rack can further include a central controller that controls (e.g., via a compiler running on the central controller) operations of each cuboid structure 900 in the rack. If the data center features a threshold power budget for an entire rack, each cuboid structure 900 can be individually managed to allocate power among all the cuboid structures 900 in the rack. Advantageously, not only is power managed to prevent the threshold power budget to be exceeded, but the quality of service (QOS) across each cuboid structure 900 in the rack is also maintained.
Example Process Flow for Integrated Circuit with Tile Structures
The operations of method 1000 can be initiated by a compiler operating on at least one computer processor and/or on a host server separate from the integrated circuit. The compiler can utilize as its input a model (e.g., a machine learning model) for the deterministic streaming processor and outputs instructions for configuring operation of the deterministic streaming processor and the integrated circuit as a whole. The integrated circuit initiates 1005 issuance of instructions for execution by processing units (e.g., computational elements of one or more functional slices) across a plurality of dies of one or more tile structures of the integrated circuit. The integrated circuit initiates 1010 streaming of data through the processing units across the plurality of dies of the one or more tile structures for execution of the instructions. The integrated circuit initiates 1015 returning of resulting data to one or more memory slices of the one or more tile structures.
Embodiments of the present disclosure further relate to a die-to-die (D2D) dense packaging of deterministic streaming processors (e.g., TSPs). Each deterministic streaming processor (e.g., TSP) connected in a D2D structure features an extended scalable compute architecture suitable for running the next generation of artificial intelligence/machine learning algorithms. Each deterministic streaming processor of the D2D structure can support SIMD operations (e.g., 256 byte SIMD operations) with spatial pipeline processing, streaming S (e.g., S=64) concurrent streams per superlane, and feature more than, e.g., 130 TB/s of memory bandwidth. Each deterministic streaming processor in the D2D structure can further support a deterministic High-Bandwidth Memory (HBM) that is stride insensitive and features a massive concurrency (e.g., 1.5 TB/s of HBM bandwidth). Each deterministic streaming processor in the D2D structure can include four MXM engines each supporting 256×256 fused dot product computations, doubled FP16 (16-bit floating point) density, and features additional support for INT4 (4-bit integer) operations. Each deterministic streaming processor in the D2D structure can further include programmable high performance VXMs, e.g., 8192 vector ALUs, SXMs with doubled permutters for improved data movement and data reshaping, and ICUs with multiple instruction queues for achieving instruction parallelism. Each deterministic streaming processor in the D2D structure can support extensible network scalability and multiple D2D topologies.
In one embodiment, the D2D interface 1115 represents an interface for mapping of 16 superlanes of between the dies 1105 and 1110. In such case, the D2D interface 1115 can support the streaming rate of up to 2 TB/sec. In another embodiment, the D2D interface 1115 represents an interface for mapping of 24 superlanes between the dies 1105 and 1110. In such case, the D2D interface 1115 can achieve the streaming rate of up to 3 TB/sec. A size of the D2D structure 1100 along horizontal direction (e.g., x direction) can be, e.g., 65 mm or 85 mm; and a size of the D2D structure 1100 along vertical direction (e.g., y direction) can be, e.g., 65 mm or 85 mm. The D2D structure 1100 can support, e.g., FP16 data format for achieving 2 PetaFlops (floating point operations), INT8 data format for achieving 4 PetaOps, and INT4 data format for achieving 8 PetaOps. The D2D structure 1100 can also include, e.g., 480 MBytes of SRAM.
Each die 1105, 1110 (e.g., each TSP core) of the D2D structure 1100 can include a deterministic HBM that provides, e.g., 1.6 TB/s of stream bandwidth into a local DRAM of the respective die 1105, 1110. Each die 1105, 1110 can be designed to support, e.g., 64-byte word size. The D2D structure 1100 can support a predictable and scalable low latency interconnection networks (e.g., on-chip and off-chip). The D2D structure 1100 can further support energy-proportionality to take advantage of the dynamic power range.
The D2D structure 1200 can support dense packaging of additional dies along vertical direction (e.g., y direction). Additionally or alternatively, the D2D structure 1200 can support dense packaging on a substrate of one or more dies of the D2D structure 1200. The D2D structure 1200 can support extension of a fast SRAM memory capacity and provides a path for very efficient model-parallelism across multiple dies. A latency across any D2D interface of the D2D structure 1200 can be only, e.g., 18 clock cycles (or 9 ns), while transferring S streams (e.g., S=4) in each direction every clock cycle. A bit error rate (BER) of any D2D interface of the D2D structure 1200 can be less than 10−20, which makes D2D interfaces of the D2D structure 1200 robust and as reliable as a wire. The D2D structure 1200 is configured to function as a single core processor for model-parallelism across the dies 12051, 12052, . . . , 1205N.
The D2D structure 1330 can be converted into a D2D structure 1345 having the D2D folded mesh configuration (e.g., radix-4 mesh). A D2D interface 13500 maps superlanes of the die 13350 to superlanes of the die 13351 along vertical direction (e.g., y direction); a D2D interface 13501 maps superlanes of the die 13351 superlanes of the die 13352 along vertical direction (e.g., y direction); and a D2D interface 13502 maps superlanes of the die 13352 superlanes of the die 13353 along vertical direction (e.g., y direction). In comparison with the D2D structure 1330, the D2D structure 1345 can achieve the same streaming bandwidth while having a smaller overall size. A size of the D2D structure 1345 along horizontal direction (e.g., x direction) can be, e.g., 55 mm, and a size of the D2D structure 1345 along vertical direction (e.g., y direction) can be, e.g., 55 mm. Similar as the D2D structure 1330, the D2D structure 1345 is configured to function as a single core processor for model-parallelism across the dies 13350, 13351, 13352, 13353.
The array of super cells 1405 can be implemented as a two-dimensional array of N super cells (e.g., N=4). Each supper cell in the array of super cells 1405 can include on-chip stream registers for storing data that are streaming via the D2D interface 1410. The array of super cells 1405 can provide a streaming bandwidth in the order of, e.g., hundreds of TB/sec. The array of super cells 1405 are directly connected to superlanes of the first die (not shown in
Each superlane 1415 and a corresponding portion of the D2D interface 1410 can stream, e.g., 256 bits in each direction (e.g., along x axis), including S streams (e.g., S=4) per supelane every clock cycle. The D2D interface 1410 can support, e.g., up to 4.6 TBytes/sec on each hemisphere of a TSP core for a total bandwidth of, e.g., 9 TB/sec. The D2D interface 1410 can be placed on both hemispheres of the TSP core to allow for physical and data streaming symmetry.
The D2D interface 1410 illustrated in
The D2D mapping structure 1400 with the D2D interface 1410 allows both face-to-face (F2F) and back-to-back (B2B) die orientation when stacking multiple dies into a D2D configuration. The D2D mapping structure 1400 enables three-dimensional packaging with system-in-package having, e.g., the radix-4 mesh configuration and radix-8 torus configuration. The D2D mapping structure 1400 also allows efficient model parallelism within the system-in package, which can exploit nearest-neighbor communication patterns. The D2D mapping structure 1400 provides a preferred communication hierarchy to each die connected in the D2D configuration, e.g., in the order of hundreds of TB/sec on-chip stream registers bandwidth, in the order of tens of TB/sec D2D streaming bandwidth, and in the order of TB/sec of an off-chip network bandwidth.
The die 1520 can also support a relatively low supply voltage and a low clock frequency for efficiency of operations. Optionally, the die 1520 can include two 32b channels Low-Power Double Data Rate (LPDDR) memory placed in each corner of the die 1520. In some embodiments (not shown in
Embodiments of the present disclosure are directed to a novel approach to building “network-in-package” using the D2D interfacing. The packaging scheme presented herein allows building a multi-chip module with multiple dies “side by side” or to “vertically stack” the dies by “folding” the dies. This packaging scheme extends the “streaming” programming model across multiple chips (or dies) as streams automatically flow from one chip (i.e., die) to the next in either the East direction or West direction. The physical symmetry of D2D interface placement at East/West edge of the die allows treating the die as “edge symmetric” and allows “flipping” the die upside-down in order to “stack” on top of its adjacent die. The edge-symmetry allows adjacent dies to be stacked “face-to-face” or “back-to-back”. The edge symmetry enables the packaging of otherwise horizontal dies and allows building of “network of TSPs” within the package, such as generating “folded mesh” to include, e.g., four TSP cores into a single 45×45 mm package.
The D2D package (or D2D structure) operates as a single “functional unit” with a control that is simplified to passing S streams (e.g., S=4 streams) across each D2D interface macro when, e.g., the “valid” (propagate) bit is set. The packaging scheme presented herein allows activations to be streamed across multiple chips extremely efficiently with only a handful of cycles latency, e.g., for achieving of more than TBytes/sec of bandwidth with a limited control/instruction overhead. The packaging scheme presented herein further allows treating the M×Ms across multiple chips (i.e., multiple TSP cores) in the D2D package as “asymmetric” since the M×Ms would be of size, e.g., 256×512 or 256×768 if connected to two or three dies (or TSP chips) in the D2D package, respectively. The packaging scheme presented herein further allows synchronous streaming between the dies (or TSP chips), which truly extends the deterministic fixed-latency streaming model.
Example Process Flow for Integrated Circuit with Die-to-Die Dense Packaging
The operations of method 1600 can be initiated by a compiler operating on the at least one computer processor (e.g., as part of the integrated circuit) and/or on a host server (e.g., separate from the integrated circuit). The compiler can utilize as its input a model (e.g., a machine learning model) for deterministic streaming processors and outputs instructions for configuring operation of the integrated circuit with the plurality of dies connected in the D2D structure.
The integrated circuit initiates 1605 (e.g., via the compiler), issuance of a plurality of instructions for execution by a plurality of processing units across a first die and a second die, the second die connected to the first die via a D2D interface circuit in a D2D configuration forming the D2D structure with the first die. The integrated circuit initiates 1610 (e.g., via the compiler) streaming of data between a first plurality of superlanes of the first die and a second plurality of superlanes of the second die via the D2D interface circuit along a first direction or a second direction orthogonal to the first direction for execution of the plurality of instructions.
The integrated circuit can initiate (e.g., via the compiler) streaming of data across a plurality of dies along at least one of the first direction and the second direction, the plurality of dies connected in the D2D configuration via a plurality of D2D interface circuits and forming the D2D structure. The integrated circuit can configure (e.g., via the compiler) the plurality of dies forming the D2D structure to function as a single core processor for model-parallelism across the plurality of dies of the D2D structure.
In some embodiments, the D2D interface circuit comprises a plurality of bidirectional interface slices, and a pair of the bidirectional interface slices is connected to a corresponding superlane of the second plurality of superlanes of the second die. The D2D interface circuit further comprises a D2D core interface circuit connected to a corresponding subset of the first plurality of superlanes of the first die.
In some embodiments, the D2D interface circuit comprises a plurality of D2D interface banks, each of the plurality of D2D interface banks connecting a cluster of the first plurality of superlanes to a cluster of the second plurality of superlanes. A size of each of the plurality of D2D interface banks of the D2D interface along the first direction matches a size of the cluster of the second plurality of superlanes along the first direction. Each of the plurality of D2D interface banks of the D2D interface comprises a plurality of D2D interface macros, and each of the plurality of D2D interface macros comprises a respective bidirectional interface slice of the plurality of bidirectional interface slices.
The D2D structure can further include one more dies connected with the first and second dies in the D2D configuration and spanning across at least one of the first dimension and the second dimension. The D2D structure can be configured to function as a single core processor for model-parallelism across a plurality of dies of the D2D structure. The plurality of dies of the D2D structure can be connected in a D2D folded mesh configuration or a D2D torus configuration.
The integrated circuit can further include a third die connected to the second die via a second D2D interface circuit in the D2D configuration forming the D2D structure with the first and second dies, the second D2D interface connecting the second plurality of superlanes of the second die to a third plurality of superlanes of the third die for streaming data between the second die and the third die along the first direction or the second direction. The integrated circuit can further include a fourth die connected to the third die via a third D2D interface circuit in the D2D configuration forming the D2D structure with the first, second and third dies, the third D2D interface connecting the third plurality of superlanes of the third die to a fourth plurality of superlanes of the fourth die for streaming data between the third die and the fourth die along the first direction or the second direction. The first, second, third and fourth dies that form the D2D structure can be mutually connected in a D2D folded mesh configuration. The first, second, third and fourth dies connected in the D2D folded mesh configuration are configured to operate as a single core processor for model-parallelism across the D2D folded mesh configuration.
The first die can comprise a first TSP having a first plurality of functional units connected at least in part via the first plurality of superlanes, and the second die comprises a second TSP having a second plurality of functional units connected at least in part via the second plurality of superlanes, a high-bandwidth memory, and the D2D interface circuit. The second die can be connected to the first die in a back-to-back configuration or in a face-to-face configuration forming the D2D structure.
In
The computer system can be structured as a server, a client, a workstation, a mainframe, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a smartphone, a web appliance, a rack-mounted ‘blade’, a kiosk, a television, a game station, a network router, switch or bridge, or any data processing machine with instructions that specify actions to be taken by that machine. The term ‘server’, as used herein, refers to a computer or processor that typically performs processes for, and sends data and information to, another computer or processor.
A computer system typically is structured, in part, with at least one operating system program, for example, MICROSOFT WINDOWS, APPLE MACOS and IOS, GOOGLE ANDROID, Linux and/or Unix. The computer system typically includes a Basic Input/Output System (BIOS) and processor firmware. The operating system, BIOS and firmware are used by the processor to structure and control any subsystems and interfaces connected to the processor. Example processors that enable these operating systems include: the Pentium, Itanium, and Xeon processors from INTEL; the Opteron and Athlon processors from AMD (ADVANCED MICRO DEVICES); the Graviton processor from AMAZON; the POWER processor from IBM; the SPARC processor from ORACLE; and the ARM processor from ARM Holdings.
Any embodiment of the present disclosure is limited neither to an electronic digital logic computer structured with programs nor to an electronically programmable device. For example, the claimed embodiments can use an optical computer, a quantum computer, an analog computer, or the like. Further, where only a single computer system or a single machine is signified, the use of a singular form of such terms also can signify any structure of computer systems or machines that individually or jointly use processes. Due to the ever-changing nature of computers and networks, the description of computer system 1710 depicted in
Network interface subsystem 1716 provides an interface to outside networks, including an interface to communication network 1718, and is coupled via communication network 1718 to corresponding interface devices in other computer systems or machines. Communication network 1718 can comprise many interconnected computer systems, machines and physical communication connections (signified by ‘links’). These communication links can be wireline links, optical links, wireless links (e.g., using the WiFi or Bluetooth protocols), or any other physical devices for communication of information. Communication network 1718 can be any suitable computer network, for example a wide area network such as the Internet, and/or a local-to-wide area network such as Ethernet. The communication network is wired and/or wireless, and many communication networks use encryption and decryption processes, such as is available with a virtual private network. The communication network uses one or more communications interfaces, which receive data from, and transmit data to, other systems. Embodiments of communications interfaces typically include an Ethernet card, a modem (e.g., telephone, satellite, cable, or Integrated Services Digital Network (ISDN)), (asynchronous) digital subscriber line (DSL) unit, Firewire interface, universal serial bus (USB) interface, and the like. Communication algorithms (‘protocols’) can be specified using one or communication languages, such as Hypertext Transfer Protocol (HTTP), Transmission Control Protocol/Internet Protocol (TCP/IP), Real-time Transport Protocol/Real Time Streaming Protocol (RTP/RTSP), Internetwork Packet Exchange (IPX) protocol and/or User Datagram Protocol (UDP).
User interface input devices 1722 can include an alphanumeric keyboard, a keypad, pointing devices such as a mouse, trackball, toggle switch, touchpad, stylus, a graphics tablet, an optical scanner such as a bar code reader, touchscreen electronics for a display device, audio input devices such as voice recognition systems or microphones, eye-gaze recognition, brainwave pattern recognition, optical character recognition systems, and other types of input devices. Such devices are connected by wire or wirelessly to a computer system. Typically, the term ‘input device’ signifies all possible types of devices and processes to transfer data and information into computer system 1710 or onto communication network 1718. User interface input devices typically enable a user to select objects, icons, text and the like that appear on some types of user interface output devices, for example, a display subsystem.
User interface output devices 1720 can include a display subsystem, a printer, a fax machine, or a non-visual communication device such as audio and haptic devices. The display subsystem can include a CRT, a flat-panel device such as an LCD, an image projection device, or some other device for creating visible stimuli such as a virtual reality system. The display subsystem can also provide non-visual stimuli such as via audio output, aroma generation, or tactile/haptic output (e.g., vibrations and forces) devices. Typically, the term ‘output device’ signifies all possible types of devices and processes to transfer data and information out of computer system 1710 to the user or to another machine or computer system. Such devices are connected by wire or wirelessly to a computer system. Note that some devices transfer data and information both into and out of the computer, for example, haptic devices that generate vibrations and forces on the hand of a user while also incorporating sensors to measure the location and movement of the hand. Technical applications of the sciences of ergonomics and semiotics are used to improve the efficiency of user interactions with any processes and computers disclosed herein, such as any interactions with regards to the design and manufacture of circuits that use any of the above input or output devices.
Memory subsystem 1726 typically includes several memories including a main RAM 1730 (or other volatile storage device) for storage of instructions and data during program execution and a ROM 1732 in which fixed instructions are stored. File storage subsystem 1728 provides persistent storage for program and data files, and can include a hard disk drive, a floppy disk drive along with associated removable media, a CD-ROM drive, an optical drive, a flash memory such as a USB drive, or removable media cartridges. If computer system 1710 includes an input device that performs optical character recognition, then text and symbols printed on a physical object (such as paper) can be used as a device for storage of program and data files. The databases and modules used by some embodiments can be stored by file storage subsystem 1728.
Bus subsystem 1712 provides a device for transmitting data and information between the various components and subsystems of computer system 1710. Although bus subsystem 1712 is depicted as a single bus, alternative embodiments of the bus subsystem can use multiple buses. For example, a main memory using RAM can communicate directly with file storage systems using DMA systems.
By way of example,
The structure of a computing machine described in
The example computer system 1800 includes one or more processors (generally, a processor 1802) (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), one or more application specific integrated circuits (ASICs), one or more radio-frequency integrated circuits (RFICs), or any combination of these), a main memory 1804, and a static memory 1806, which are configured to communicate with each other via a bus 1808. The computer system 1800 can further include graphics display unit 1810 (e.g., a plasma display panel (PDP), a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)). The computer system 1800 can also include alphanumeric input device 1812 (e.g., a keyboard), a cursor control device 1814 (e.g., a mouse, a trackball, a joystick, a motion sensor, or other pointing instrument), a storage unit 1816, a signal generation device 1818 (e.g., a speaker), and a network interface device 1820, which also are configured to communicate via the bus 1808.
The storage unit 1816 includes a computer-readable medium 1822 on which the instructions 1824 are stored embodying any one or more of the methodologies or functions described herein. The instructions 1824 can also reside, completely or at least partially, within the main memory 1804 or within the processor 1802 (e.g., within a processor's cache memory). Thus, during execution thereof by the computer system 1800, the main memory 1804 and the processor 1802 can also constitute computer-readable media. The instructions 1824 can be transmitted or received over a network 1826 via the network interface device 1820.
While the computer-readable medium 1822 is shown in an example embodiment to be a single medium, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) able to store instructions (e.g., the instructions 1824). The computer-readable medium 1822 can include any medium that is capable of storing instructions (e.g., the instructions 1824) for execution by the machine and that cause the machine to perform any one or more of the methodologies disclosed herein. The computer-readable medium 1822 can include, but not be limited to, data repositories in the form of solid-state memories, optical media, and magnetic media. The computer-readable medium 1822 does not include a transitory medium such as a signal or a carrier wave.
The disclosed configurations can have benefits and advantages that include, for example, a more efficient data flow by separating the functions of the processor into specialized functional units, and configuring the timing of data and instructions to each functional unit, such that each unit is able operate on received data based upon a known timing between received data and instructions. Because the compiler for the processor is hardware aware, it is able to configure an explicit plan for the processor indicating how and when instructions and data operands are transmitted to different tiles of the processor. By accounting for the timing of received instructions and data, the data can be transmitted between the tiles of the processor without unnecessary metadata, increasing the efficiency of the transmission. In addition, by separating the transmission of data and instructions, instructions can be iterated and looped independent of received data operands.
In addition, because each computational element of the processor is dedicated to a specific function (e.g., MEM, VXM, MXM, SXM), the amount of instructions needed to be processed by the computational elements can be reduced. For example, certain computational elements (e.g., in MXM functional slice) can be configured to perform a limited set of operations on any received data. As such, these computational elements can be able to operate without having to receive explicit instructions or only receiving intermittent or limited instructions, potentially simplifying operation of the processor. For example, data operands read from memory can be intercepted by multiple functional slices as the data is transmitted across a data lane, allowing for multiple operations to be performed on the data in a more efficient manner.
In operation, a host computer programs a DMA engine to actually transfer data, again all of which is coordinated by the runtime layer. Specifically, the IDU transfers 320-byte vectors from PCIe-Gen4 32-bytes every core-clock cycle (e.g., nominal 900 Mhz). Thus, the 320-element vector arrives over a period of 10 cycles and placed on multiple streams moving towards the MEM. The incoming streams flow on S24-31 (upper eight streams), from which the MEM performs a “write” to commit that vector to SRAM. Hence, a PCI-Receive consists of (i) receiving the data from the PCI interface, and (ii) writing the vector into the specified functional slice of the MEM.
The foregoing description of the embodiments of the disclosure has been presented for the purpose of illustration; it is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above disclosure.
Some portions of this description describe the embodiments of the disclosure in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are commonly used by those skilled in the data processing arts to convey the substance of their work effectively to others skilled in the art. These operations, while described functionally, computationally, or logically, are understood to be implemented by computer programs or equivalent electrical circuits, microcode, or the like. Furthermore, it has also proven convenient at times, to refer to these arrangements of operations as modules, without loss of generality. The described operations and their associated modules can be embodied in software, firmware, hardware, or any combinations thereof.
Any of the steps, operations, or processes described herein can be performed or implemented with one or more hardware or software modules, alone or in combination with other devices. In one embodiment, a software module is implemented with a computer program product comprising a computer-readable medium containing computer program code, which can be executed by a computer processor for performing any or all of the steps, operations, or processes described.
Embodiments of the disclosure can also relate to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, and/or it can comprise a general-purpose computing device selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a non-transitory, tangible computer readable storage medium, or any type of media suitable for storing electronic instructions, which can be coupled to a computer system bus. Furthermore, any computing systems referred to in the specification can include a single processor or can be architectures employing multiple processor designs for increased computing capability.
Some embodiments of the present disclosure can further relate to a system comprising a processor (e.g., a tensor streaming processor or an artificial intelligence processor), at least one computer processor (e.g., a host server), and a non-transitory computer-readable storage medium. The storage medium can store computer executable instructions, which when executed by the compiler operating on the at least one computer processor, cause the at least one computer processor to be operable for performing the operations and techniques described herein.
Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the disclosure be limited not by this detailed description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of the embodiments is intended to be illustrative, but not limiting, of the scope of the disclosure, which is set forth in the following claims.
The subject patent application is a U.S. National Stage filing under 35 U.S.C. § 371 of International Patent Cooperation Treaty (PCT) Application No. PCT/US2023/013535, filed Feb. 21, 2023, and entitled “DIE-TO-DIE DENSE PACKAGING OF DETERMINISTIC STREAMING PROCESSORS,” which application claims the priority and benefit to U.S. Provisional Patent Application Ser. No. 63/312,781, filed Feb. 22, 2022, which applications are hereby incorporated by reference in their entireties herein.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2023/013535 | 2/21/2023 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63312781 | Feb 2022 | US |
