comprising clock generation or timing circuitry

Industry

CPC
G11C29/12015

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/12015comprising clock generation or timing circuitry

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Techniques for initializing memory error correction
- Patent number 12,170,122
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Kai Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device including command log register and comm...
- Patent number 12,170,121
- Issue date Dec 17, 2024
- Samsung Electronics Co., Ltd.
- Youngsan Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test circuit, memory array, and testing method of memory array
- Patent number 12,170,123
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Test systems configured to perform test mode operations for multipl...
- Patent number 12,159,681
- Issue date Dec 3, 2024
- SK hynix Inc.
- Sang Ah Hyun
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing method and testing system
- Patent number 12,154,641
- Issue date Nov 26, 2024
- NANYA TECHNOLOGY CORPORATION
- Wei-Chun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed synchronous write-through operation for testing two-port m...
- Patent number 12,148,490
- Issue date Nov 19, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and operating method thereof
- Patent number 12,142,331
- Issue date Nov 12, 2024
- SK hynix Inc.
- Seung Yeol Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for parallel memory test
- Patent number 12,142,337
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Nitesh Mishra
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method, computer apparatus, and computer-readable storage medium
- Patent number 12,112,817
- Issue date Oct 8, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Biao Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device detecting defect, and operating method...
- Patent number 12,100,463
- Issue date Sep 24, 2024
- Samsung Electronics Co., Ltd.
- Bongkil Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic memory device
- Patent number 12,040,036
- Issue date Jul 16, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chia-Hsiang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit and test method thereof
- Patent number 12,033,709
- Issue date Jul 9, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liang Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Monitoring and adjusting access operations at a memory device
- Patent number 12,014,792
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Mark D. Ingram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware accelerator device, corresponding system and method of ope...
- Patent number 11,996,158
- Issue date May 28, 2024
- STMicroelectronics S.r.l.
- Giampiero Borgonovo
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with selective command delay and associated me...
- Patent number 11,990,195
- Issue date May 21, 2024
- Boon Hor Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Base die, memory system, and semiconductor structure
- Patent number 11,978,525
- Issue date May 7, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Shu-Liang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking and refreshing state metrics in memory sub-systems
- Patent number 11,955,194
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Michael Sheperek
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing circuit, testing device and testing method thereof
- Patent number 11,948,650
- Issue date Apr 2, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liang Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal generation circuit and method, and semiconductor memory
- Patent number 11,935,608
- Issue date Mar 19, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for tuning an external memory interface
- Patent number 11,935,613
- Issue date Mar 19, 2024
- Texas Instruments Incorporated
- Zachary John Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for recovery for memory systems and memory systems employin...
- Patent number 11,929,133
- Issue date Mar 12, 2024
- Micron Technology, Inc.
- Rachael Skreen
- G11 - INFORMATION STORAGE
Information Patent Grant
Debug capabilities of a memory system with a pin
- Patent number 11,923,023
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Jingwei Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus, memory device, and method reducing clock training time
- Patent number 11,923,042
- Issue date Mar 5, 2024
- Samsung Electronics Co., Ltd.
- Sangwoo Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for testing of memory
- Patent number 11,923,024
- Issue date Mar 5, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Xiaoxiao Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system including a sub-controller and operating method of th...
- Patent number 11,901,027
- Issue date Feb 13, 2024
- SK Hynix Inc.
- Jong Joo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective margin testing to determine whether to signal train a mem...
- Patent number 11,894,084
- Issue date Feb 6, 2024
- Intel Corporation
- Dujian Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, device, and circuit for high-speed memories
- Patent number 11,894,086
- Issue date Feb 6, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jaspal Singh Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Quick reliability scan for memory device
- Patent number 11,875,868
- Issue date Jan 16, 2024
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-repair for sequential SRAM
- Patent number 11,869,617
- Issue date Jan 9, 2024
- Meta Platforms Technologies, LLC
- Huichu Liu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR SYSTEM FOR PERFORMING READ-MODIFY-WRITE OPERATION
- Publication number 20240420752
- Publication date Dec 19, 2024
- SK HYNIX INC.
- Woongrae KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-CALIBRATION IN A MEMORY DEVICE
- Publication number 20240420789
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Jennifer E. Taylor
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM INTERNAL DFT CIRCUIT WITHOUT OUTPUT HOLD DEGRADATION
- Publication number 20240412794
- Publication date Dec 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yoshisato Yokoyama
- G11 - INFORMATION STORAGE
Information Patent Application
Fully Scannable Memory Arrays
- Publication number 20240412797
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Scanning a Memory Array
- Publication number 20240412798
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR HANDLING FOR REPROJECTION TIMELINE
- Publication number 20240386980
- Publication date Nov 21, 2024
- QUALCOMM Incorporated
- Simon Peter William BOOTH
- G11 - INFORMATION STORAGE
Information Patent Application
Magnetic Memory Device
- Publication number 20240331796
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-Hsiang CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
TEST METHOD FOR TESTING DECISION FEEDBACK EQUALIZATION OF MEMORY DE...
- Publication number 20240331791
- Publication date Oct 3, 2024
- NANYA TECHNOLOGY CORPORATION
- Yi-Hsuan Chu
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH SLOW VOLTAGE RAMP COMPENSATION
- Publication number 20240321379
- Publication date Sep 26, 2024
- SANDISK TECHNOLOGIES LLC
- Sai Gautham Thoppa
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED ME...
- Publication number 20240304269
- Publication date Sep 12, 2024
- Lodestar Licensing Group LLC
- Boon Hor Lam
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE DETECTING DEFECT OF WORD LINE PATH AND OPERATING METH...
- Publication number 20240296898
- Publication date Sep 5, 2024
- Samsung Electronics Co., Ltd.
- Taehong KWON
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF TESTING REPAIR CIRCUITS OF MEMORY DEVICES
- Publication number 20240290414
- Publication date Aug 29, 2024
- Samsung Electronics Co., Ltd.
- Taewon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHOD
- Publication number 20240274214
- Publication date Aug 15, 2024
- Integrated Silicon Solution Inc.
- Hyeon Jae LEE
- G11 - INFORMATION STORAGE
Information Patent Application
TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS
- Publication number 20240265989
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Michael Sheperek
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND ADDRESS CONTROL CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SE...
- Publication number 20240257891
- Publication date Aug 1, 2024
- SK HYNIX INC.
- Ji Hwan PARK
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Bank Architecture with Latches
- Publication number 20240249790
- Publication date Jul 25, 2024
- ARM Limited
- Yannis Jallamion-Grive
- G11 - INFORMATION STORAGE
Information Patent Application
TEST CIRCUIT AND RECEIVING CIRCUIT HAVING TEST FUNCTION
- Publication number 20240242773
- Publication date Jul 18, 2024
- SK HYNIX INC.
- Gi Moon HONG
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR TUNING AN EXTERNAL MEMORY INTERFACE
- Publication number 20240233855
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Zachary John BROWN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF TH...
- Publication number 20240212779
- Publication date Jun 27, 2024
- SK HYNIX INC.
- Jong Joo LEE
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR RECOVERY FOR MEMORY SYSTEMS AND MEMORY SYSTEMS EMPLOYIN...
- Publication number 20240185941
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Rachael Skreen
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING METHOD AND TESTING SYSTEM
- Publication number 20240177790
- Publication date May 30, 2024
- NANYA TECHNOLOGY CORPORATION
- Wei-Chun CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INTERFACE AND SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR...
- Publication number 20240170085
- Publication date May 23, 2024
- Samsung Electronics Co., Ltd.
- Hojun YOON
- G11 - INFORMATION STORAGE
Information Patent Application
TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPL...
- Publication number 20240161851
- Publication date May 16, 2024
- SK HYNIX INC.
- Sang Ah HYUN
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, DEVICE, AND CIRCUIT FOR HIGH-SPEED MEMORIES
- Publication number 20240153573
- Publication date May 9, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaspal Singh SHAH
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
- Publication number 20240127901
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Daniel S. Miller
- G11 - INFORMATION STORAGE
Information Patent Application
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- Publication number 20240120016
- Publication date Apr 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR PERFORMING TEST
- Publication number 20240120015
- Publication date Apr 11, 2024
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE
- Publication number 20240105275
- Publication date Mar 28, 2024
- KIOXIA Corporation
- Kiyoe YAMASAWA
- G11 - INFORMATION STORAGE

comprising clock generation or timing circuitry

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Techniques for initializing memory error correction

Semiconductor memory device including command log register and comm...

Memory test circuit, memory array, and testing method of memory array

Test systems configured to perform test mode operations for multipl...

Testing method and testing system

At-speed synchronous write-through operation for testing two-port m...

Memory controller and operating method thereof

System and method for parallel memory test

Test method, computer apparatus, and computer-readable storage medium

Semiconductor memory device detecting defect, and operating method...

Magnetic memory device

Test circuit and test method thereof

Monitoring and adjusting access operations at a memory device

Hardware accelerator device, corresponding system and method of ope...

Semiconductor device with selective command delay and associated me...

Base die, memory system, and semiconductor structure

Single “A” latch with an array of “B” latches

Tracking and refreshing state metrics in memory sub-systems

Testing circuit, testing device and testing method thereof

Signal generation circuit and method, and semiconductor memory

Method for tuning an external memory interface

Methods for recovery for memory systems and memory systems employin...

Debug capabilities of a memory system with a pin

Apparatus, memory device, and method reducing clock training time

Method and system for testing of memory

Memory system including a sub-controller and operating method of th...

Selective margin testing to determine whether to signal train a mem...

Method, device, and circuit for high-speed memories

Quick reliability scan for memory device

Self-repair for sequential SRAM

Patents Applicationslast 30 patents

SEMICONDUCTOR SYSTEM FOR PERFORMING READ-MODIFY-WRITE OPERATION

SELF-CALIBRATION IN A MEMORY DEVICE

SRAM INTERNAL DFT CIRCUIT WITHOUT OUTPUT HOLD DEGRADATION

Fully Scannable Memory Arrays

Method for Scanning a Memory Array

ERROR HANDLING FOR REPROJECTION TIMELINE

Magnetic Memory Device

TEST METHOD FOR TESTING DECISION FEEDBACK EQUALIZATION OF MEMORY DE...

NON-VOLATILE MEMORY WITH SLOW VOLTAGE RAMP COMPENSATION

SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED ME...

MEMORY DEVICE DETECTING DEFECT OF WORD LINE PATH AND OPERATING METH...

METHODS OF TESTING REPAIR CIRCUITS OF MEMORY DEVICES

MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHOD

TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMS

COMMAND ADDRESS CONTROL CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SE...

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

Register Bank Architecture with Latches

TEST CIRCUIT AND RECEIVING CIRCUIT HAVING TEST FUNCTION

METHOD FOR TUNING AN EXTERNAL MEMORY INTERFACE

MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF TH...

METHODS FOR RECOVERY FOR MEMORY SYSTEMS AND MEMORY SYSTEMS EMPLOYIN...

TESTING METHOD AND TESTING SYSTEM

MEMORY INTERFACE AND SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR...

TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPL...

METHOD, DEVICE, AND CIRCUIT FOR HIGH-SPEED MEMORIES

TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION

AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES

SEMICONDUCTOR DEVICE AND METHOD FOR PERFORMING TEST

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE