comprising I/O circuitry

Industry

CPC
G11C29/1201

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/1201comprising I/O circuitry

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Test controller enabling a snapshot restore and resume operation wi...
- Patent number 12,205,660
- Issue date Jan 21, 2025
- SanDisk Technologies, Inc.
- Eran Moshe
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip test method and apparatus, medium, and device
- Patent number 12,198,773
- Issue date Jan 14, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Beiyou Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for testing inaccessible interface circuits i...
- Patent number 12,196,805
- Issue date Jan 14, 2025
- RAMBUS INC.
- Frederick A. Ware
- G01 - MEASURING TESTING
Information Patent Grant
Memory device sideband systems and methods
- Patent number 12,198,774
- Issue date Jan 14, 2025
- Micron Technology, Inc.
- Joshua E. Alzheimer
- G11 - INFORMATION STORAGE
Information Patent Grant
Metadata storage at a memory device
- Patent number 12,198,776
- Issue date Jan 14, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory and operation method thereof
- Patent number 12,190,935
- Issue date Jan 7, 2025
- SK Hynix Inc.
- Sang Woo Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data coding device, memory controller, and storage device
- Patent number 12,190,988
- Issue date Jan 7, 2025
- SK Hynix Inc.
- Ie Ryung Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for checking data, electronic device, and storage...
- Patent number 12,190,976
- Issue date Jan 7, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Jia Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory interface circuitry and built-in self-testing method
- Patent number 12,183,411
- Issue date Dec 31, 2024
- Integrated Silicon Solution Inc.
- Hyeon Jae Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method for testing decision feedback equalization of memory de...
- Patent number 12,176,051
- Issue date Dec 24, 2024
- NANYA TECHNOLOGY CORPORATION
- Yi-Hsuan Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for initializing memory error correction
- Patent number 12,170,122
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Kai Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self test circuit for segmented static random access memor...
- Patent number 12,170,120
- Issue date Dec 17, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Hitesh Chawla
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device including command log register and comm...
- Patent number 12,170,121
- Issue date Dec 17, 2024
- Samsung Electronics Co., Ltd.
- Youngsan Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test circuit, memory array, and testing method of memory array
- Patent number 12,170,123
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Test systems configured to perform test mode operations for multipl...
- Patent number 12,159,681
- Issue date Dec 3, 2024
- SK hynix Inc.
- Sang Ah Hyun
- G11 - INFORMATION STORAGE
Information Patent Grant
Storing memory array operational information in non-volatile subarrays
- Patent number 12,158,826
- Issue date Dec 3, 2024
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing method and testing system
- Patent number 12,154,641
- Issue date Nov 26, 2024
- NANYA TECHNOLOGY CORPORATION
- Wei-Chun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed synchronous write-through operation for testing two-port m...
- Patent number 12,148,490
- Issue date Nov 19, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and operating method thereof
- Patent number 12,142,331
- Issue date Nov 12, 2024
- SK hynix Inc.
- Seung Yeol Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing circuit for a memory device
- Patent number 12,142,332
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Chunqiang Weng
- G11 - INFORMATION STORAGE
Information Patent Grant
Health scan for content addressable memory
- Patent number 12,142,334
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Tomoko Ogura Iwasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for parallel memory test
- Patent number 12,142,337
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Nitesh Mishra
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method, computer apparatus, and computer-readable storage medium
- Patent number 12,112,817
- Issue date Oct 8, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Biao Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Read destructive memory wear leveling system
- Patent number 12,112,821
- Issue date Oct 8, 2024
- Seagate Technology LLC
- Jon D. Trantham
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory scheme capable of controlling flash memory device auto...
- Patent number 12,112,816
- Issue date Oct 8, 2024
- Silicon Motion, Inc.
- Tsu-Han Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Repairable latch array
- Patent number 12,100,464
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Joel Thornton Irby
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device detecting defect, and operating method...
- Patent number 12,100,463
- Issue date Sep 24, 2024
- Samsung Electronics Co., Ltd.
- Bongkil Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular error correction code circuitry
- Patent number 12,094,551
- Issue date Sep 17, 2024
- Intel Corporation
- Hwa Chaw Law
- G11 - INFORMATION STORAGE
Information Patent Grant
Virtualized scan chain testing in a random access memory (RAM) array
- Patent number 12,087,383
- Issue date Sep 10, 2024
- Ampere Computing LLC
- David Hoff
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-write method and apparatus for LEPS soft decoding estimation,...
- Patent number 12,088,323
- Issue date Sep 10, 2024
- Institute of Microelectronics, Chinese Academy of Sciences
- Qi Wang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST
- Publication number 20250022526
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Che Tsai
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF
- Publication number 20250022524
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- YOUNGSAN KANG
- G11 - INFORMATION STORAGE
Information Patent Application
DATA TRANSFER OVER AN INTERCONNECT BETWEEN DIES OF A THREE-DIMENSIO...
- Publication number 20250022527
- Publication date Jan 16, 2025
- Intel Corporation
- Santhosh Kumar Chandrakanthan
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE AND OPERATING METHOD OF CONTROLLER OF STORAGE DEVICE
- Publication number 20250022525
- Publication date Jan 16, 2025
- SK HYNIX INC.
- Young Gyun KIM
- G11 - INFORMATION STORAGE
Information Patent Application
TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE
- Publication number 20250014665
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Ivo Thomas Wambeke
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT
- Publication number 20250014667
- Publication date Jan 9, 2025
- ROHM CO., LTD.
- Daigo FUJIMURA
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH NEIGHBOR PLANE PROGRAM DISTURB AVOIDANCE
- Publication number 20250006288
- Publication date Jan 2, 2025
- Western Digital Technologies, Inc.
- Jiahui Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY
- Publication number 20250006285
- Publication date Jan 2, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
RECONFIGURABLE MBIST METHOD BASED ON ADAPTIVE MARCH ALGORITHM
- Publication number 20250006289
- Publication date Jan 2, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G11 - INFORMATION STORAGE
Information Patent Application
HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING
- Publication number 20250006290
- Publication date Jan 2, 2025
- ADVANCED MICRO DEVICES, INC.
- Nehal Patel
- G11 - INFORMATION STORAGE
Information Patent Application
ABORTED OPERATION DETECTION FOR NONVOLATILE MEMORY WITH NON-UNIFORM...
- Publication number 20240428874
- Publication date Dec 26, 2024
- Western Digital Technologies, Inc.
- Huiwen Xu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR TESTING MEMORY DEVICE
- Publication number 20240420788
- Publication date Dec 19, 2024
- NANYA TECHNOLOGY CORPORATION
- Yaochang CHIU
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM FOR PERFORMING READ-MODIFY-WRITE OPERATION
- Publication number 20240420752
- Publication date Dec 19, 2024
- SK HYNIX INC.
- Woongrae KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-CALIBRATION IN A MEMORY DEVICE
- Publication number 20240420789
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Jennifer E. Taylor
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-CALIBRATION IN A MEMORY DEVICE
- Publication number 20240420790
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Jennifer E. Taylor
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM INTERNAL DFT CIRCUIT WITHOUT OUTPUT HOLD DEGRADATION
- Publication number 20240412794
- Publication date Dec 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yoshisato Yokoyama
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEUR...
- Publication number 20240412796
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Fa-Long Luo
- G11 - INFORMATION STORAGE
Information Patent Application
Fully Scannable Memory Arrays
- Publication number 20240412797
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Scanning a Memory Array
- Publication number 20240412798
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
Circuits And Methods For Memory Built-In-Self-Tests
- Publication number 20240412799
- Publication date Dec 12, 2024
- Altera Corporation
- Kok Wah Khor
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING PARTIAL BLOCK PROGRAMMING USING DYNAMIC TRIM SETTINGS
- Publication number 20240412803
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Qun Su
- G11 - INFORMATION STORAGE
Information Patent Application
RUNTIME ALERT SIGNAL ACTIVATION TEST MODE
- Publication number 20240404617
- Publication date Dec 5, 2024
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES FOR DETECTING DEFECTS IN ERROR CORRECTION CIR...
- Publication number 20240404616
- Publication date Dec 5, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
DATA CLUSTERING SYSTEM AND READ VOLTAGE DETERMINATION APPARATUS FOR...
- Publication number 20240404618
- Publication date Dec 5, 2024
- SK HYNIX INC.
- Jae Yong SON
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR DETECTING AN ERROR IN AN ELECTRONIC MEMORY
- Publication number 20240386967
- Publication date Nov 21, 2024
- INSTITUT MINES TELECOM
- Jean-Max DUTERTRE
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR HANDLING FOR REPROJECTION TIMELINE
- Publication number 20240386980
- Publication date Nov 21, 2024
- QUALCOMM Incorporated
- Simon Peter William BOOTH
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURA...
- Publication number 20240379181
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Fa-Long Luo
- G11 - INFORMATION STORAGE
Information Patent Application
Interface circuit, memory controller and method for calibrating sig...
- Publication number 20240363183
- Publication date Oct 31, 2024
- SILICON MOTION, INC.
- Fu-Jen Shih
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LEVEL CELL DATA ENCODING
- Publication number 20240363184
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Win-San KHWA
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR RETIRING BLOCKS OF A MEMORY SYSTEM
- Publication number 20240363185
- Publication date Oct 31, 2024
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING

comprising I/O circuitry

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test controller enabling a snapshot restore and resume operation wi...

Memory chip test method and apparatus, medium, and device

Methods and apparatus for testing inaccessible interface circuits i...

Memory device sideband systems and methods

Metadata storage at a memory device

Memory and operation method thereof

Data coding device, memory controller, and storage device

Method and device for checking data, electronic device, and storage...

Memory interface circuitry and built-in self-testing method

Test method for testing decision feedback equalization of memory de...

Techniques for initializing memory error correction

Built-in self test circuit for segmented static random access memor...

Semiconductor memory device including command log register and comm...

Memory test circuit, memory array, and testing method of memory array

Test systems configured to perform test mode operations for multipl...

Storing memory array operational information in non-volatile subarrays

Testing method and testing system

At-speed synchronous write-through operation for testing two-port m...

Memory controller and operating method thereof

Testing circuit for a memory device

Health scan for content addressable memory

System and method for parallel memory test

Test method, computer apparatus, and computer-readable storage medium

Read destructive memory wear leveling system

Flash memory scheme capable of controlling flash memory device auto...

Repairable latch array

Semiconductor memory device detecting defect, and operating method...

Modular error correction code circuitry

Virtualized scan chain testing in a random access memory (RAM) array

Read-write method and apparatus for LEPS soft decoding estimation,...

Patents Applicationslast 30 patents

CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST

MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF

DATA TRANSFER OVER AN INTERCONNECT BETWEEN DIES OF A THREE-DIMENSIO...

STORAGE DEVICE AND OPERATING METHOD OF CONTROLLER OF STORAGE DEVICE

TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE

MEMORY CIRCUIT

NON-VOLATILE MEMORY WITH NEIGHBOR PLANE PROGRAM DISTURB AVOIDANCE

EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY

RECONFIGURABLE MBIST METHOD BASED ON ADAPTIVE MARCH ALGORITHM

HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING

ABORTED OPERATION DETECTION FOR NONVOLATILE MEMORY WITH NON-UNIFORM...

SYSTEM AND METHOD FOR TESTING MEMORY DEVICE

SEMICONDUCTOR SYSTEM FOR PERFORMING READ-MODIFY-WRITE OPERATION

SELF-CALIBRATION IN A MEMORY DEVICE

SELF-CALIBRATION IN A MEMORY DEVICE

SRAM INTERNAL DFT CIRCUIT WITHOUT OUTPUT HOLD DEGRADATION

APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEUR...

Fully Scannable Memory Arrays

Method for Scanning a Memory Array

Circuits And Methods For Memory Built-In-Self-Tests

REDUCING PARTIAL BLOCK PROGRAMMING USING DYNAMIC TRIM SETTINGS

RUNTIME ALERT SIGNAL ACTIVATION TEST MODE

SEMICONDUCTOR DEVICES FOR DETECTING DEFECTS IN ERROR CORRECTION CIR...

DATA CLUSTERING SYSTEM AND READ VOLTAGE DETERMINATION APPARATUS FOR...

METHOD FOR DETECTING AN ERROR IN AN ELECTRONIC MEMORY

ERROR HANDLING FOR REPROJECTION TIMELINE

APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURA...

Interface circuit, memory controller and method for calibrating sig...

MULTI-LEVEL CELL DATA ENCODING

TECHNIQUES FOR RETIRING BLOCKS OF A MEMORY SYSTEM