Data input circuits

Industry

CPC
G11C7/1078

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1078Data input circuits

Industries

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods employing asynchronous FIFO buffer with read...
- Patent number 12,176,064
- Issue date Dec 24, 2024
- Advanced Micro Devices, Inc.
- Richard Martin Born
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory computing method and in-memory computing apparatus
- Patent number 12,169,702
- Issue date Dec 17, 2024
- Macronix International Co., Ltd.
- Bo-Rong Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory system using standard controller component
- Patent number 12,148,462
- Issue date Nov 19, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calibrating write timing in a memory system
- Patent number 12,136,452
- Issue date Nov 5, 2024
- RAMBUS INC.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power source-synchronous signaling
- Patent number 12,119,042
- Issue date Oct 15, 2024
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock synchronizing method of a multiple clock domain memory device
- Patent number 12,057,193
- Issue date Aug 6, 2024
- Samsung Electronics Co., Ltd.
- Hye-Ran Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for input buffer power savings
- Patent number 12,046,273
- Issue date Jul 23, 2024
- Micron Technology, Inc.
- Akira Yamashita
- G11 - INFORMATION STORAGE
Information Patent Grant
Compilation method, compilation circuit, mode register and memory
- Patent number 12,046,321
- Issue date Jul 23, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Geyan Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for reducing row hammer disturbance, and a method of...
- Patent number 12,020,739
- Issue date Jun 25, 2024
- Samsung Electronics Co., Ltd.
- Sunghye Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for performing matrix operation
- Patent number 12,009,021
- Issue date Jun 11, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shih-Lien Linus Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 12,001,345
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read/write switching circuit and memory
- Patent number 11,995,341
- Issue date May 28, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- WeiBing Shang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method optimizing DQ calibration pattern for memory device and comp...
- Patent number 11,983,410
- Issue date May 14, 2024
- Samsung Electronics Co., Ltd.
- Yongseob Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR SDRAM signal calibration device and method
- Patent number 11,978,497
- Issue date May 7, 2024
- Realtek Semiconductor Corporation
- Kuo-Wei Chi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with looped-back calibration data receiver
- Patent number 11,960,344
- Issue date Apr 16, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory device with concurrent bank operations
- Patent number 11,948,629
- Issue date Apr 2, 2024
- Mosaid Technologies Incorporated
- HakJune Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic circuit, information processing apparatus, and n...
- Patent number 11,942,184
- Issue date Mar 26, 2024
- FUJIFILM Business Innovation Corp.
- Hiroaki Shiokawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,940,930
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 11,886,353
- Issue date Jan 30, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock mode determination in a memory system
- Patent number 11,880,569
- Issue date Jan 23, 2024
- Mosaid Technologies Incorporated
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 11,868,272
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for providing device status in response to read commands di...
- Patent number 11,854,655
- Issue date Dec 26, 2023
- Matthew A. Prather
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS
- Publication number 20240355378
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Akira Yamashita
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD FOR PERFORMING MATRIX OPERATION
- Publication number 20240304230
- Publication date Sep 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Lien Linus LU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR STORING PLURALITY OF DATA BITS AND METHOD OF OPER...
- Publication number 20240304225
- Publication date Sep 12, 2024
- SK HYNIX INC.
- Tae Hun PARK
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ/WRITE SWITCHING CIRCUIT AND MEMORY
- Publication number 20240256174
- Publication date Aug 1, 2024
- Changxin Memory Technologies, Inc.
- WeiBing SHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND OPERATION METHOD THEREOF
- Publication number 20240232012
- Publication date Jul 11, 2024
- Samsung Electronics Co., Ltd.
- Seongmuk KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DI...
- Publication number 20240203464
- Publication date Jun 20, 2024
- Lodestar Licensing Group LLC
- Matthew A. Prather
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ADVERTISEMENT TRANSMISSION AND DISPLAY
- Publication number 20240169395
- Publication date May 23, 2024
- STRATOSAUDIO, INC.
- Kelly M. Christensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20240168636
- Publication date May 23, 2024
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY
- Publication number 20240162156
- Publication date May 16, 2024
- Micron Technology, Inc.
- Lei Wei
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT
- Publication number 20240144992
- Publication date May 2, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DIE TERMINATION CONFIGURATION FOR INTEGRATED CIRCUIT
- Publication number 20240144982
- Publication date May 2, 2024
- Yangtze Memory Technologies Co., Ltd.
- Debo Wei
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR ADDITION AND SUBTRACTION IN MEMRISTOR-BASED I...
- Publication number 20240127888
- Publication date Apr 18, 2024
- The University of Hong Kong
- Yuan REN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20240078190
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20240028523
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20240020242
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT TAGS
- Publication number 20240004800
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
- Publication number 20230410880
- Publication date Dec 21, 2023
- Rambus Inc.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20230401162
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20230384935
- Publication date Nov 30, 2023
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20230342305
- Publication date Oct 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM
- Publication number 20230333991
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Data input circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus for allocation in a victim cache system

Apparatus and methods employing asynchronous FIFO buffer with read...

In-memory computing method and in-memory computing apparatus

Methods and apparatus for read-modify-write support in multi-banked...

High capacity memory system using standard controller component

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Method and apparatus for calibrating write timing in a memory system

Low-power source-synchronous signaling

Methods and apparatus for eviction in dual datapath victim cache sy...

Methods and apparatus to facilitate read-modify-write support in a...

Clock synchronizing method of a multiple clock domain memory device

Apparatuses and methods for input buffer power savings

Compilation method, compilation circuit, mode register and memory

Memory device for reducing row hammer disturbance, and a method of...

Victim cache with write miss merging

Device and method for performing matrix operation

Victim cache that supports draining write-miss entries

Read/write switching circuit and memory

Method optimizing DQ calibration pattern for memory device and comp...

DDR SDRAM signal calibration device and method

Memory controller with looped-back calibration data receiver

Non-volatile memory device with concurrent bank operations

Programmable logic circuit, information processing apparatus, and n...

Methods and apparatus to reduce read-modify-write cycles for non-al...

Methods and apparatus to facilitate atomic operations in victim cache

Hybrid victim cache and write miss buffer with fence operation

Clock mode determination in a memory system

Methods and apparatus for allocation in a victim cache system

Methods for providing device status in response to read commands di...

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS

DEVICE AND METHOD FOR PERFORMING MATRIX OPERATION

MEMORY DEVICE FOR STORING PLURALITY OF DATA BITS AND METHOD OF OPER...

VICTIM CACHE WITH WRITE MISS MERGING

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

READ/WRITE SWITCHING CIRCUIT AND MEMORY

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

MEMORY DEVICE AND OPERATION METHOD THEREOF

METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DI...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

SYSTEM AND METHOD FOR ADVERTISEMENT TRANSMISSION AND DISPLAY

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY

HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

ON-DIE TERMINATION CONFIGURATION FOR INTEGRATED CIRCUIT

SYSTEM AND METHOD FOR ADDITION AND SUBTRACTION IN MEMRISTOR-BASED I...

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

WRITE MERGING ON STORES WITH DIFFERENT TAGS

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM