Data input latches

Industry

CPC
G11C7/1087

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1087Data input latches

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory core characteristic screening method and system thereof
- Patent number 12,260,930
- Issue date Mar 25, 2025
- Integrated Silicon Solution Inc.
- Jeong Ho Bang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device including internal transmission path and stack...
- Patent number 12,260,929
- Issue date Mar 25, 2025
- SK Hynix Inc.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplication-and-accumulation circuits and processing-in-memory d...
- Patent number 12,254,284
- Issue date Mar 18, 2025
- SK hynix Inc.
- Choung Ki Song
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Folding ordering scheme for improved throughput in non-volatile memory
- Patent number 12,249,396
- Issue date Mar 11, 2025
- SanDisk Technologies, Inc.
- Abhinandan Venugopal
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiving circuit, data receiving system and memory device
- Patent number 12,237,042
- Issue date Feb 25, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including an interface circuit connecting a controlle...
- Patent number 12,237,046
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Youngmin Jo
- G11 - INFORMATION STORAGE
Information Patent Grant
Acceleration of in-memory-compute arrays
- Patent number 12,230,361
- Issue date Feb 18, 2025
- Apple Inc.
- Paolo Di Febbo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with input/output data rate alignment
- Patent number 12,229,435
- Issue date Feb 18, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory component having internal read-modify-write operation
- Patent number 12,223,207
- Issue date Feb 11, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage device and operating method with multiple channels
- Patent number 12,217,821
- Issue date Feb 4, 2025
- SK Hynix Inc.
- Seung Han Ryu
- G11 - INFORMATION STORAGE
Information Patent Grant
Processing-in-memory devices having multiplication-and-accumulation...
- Patent number 12,217,019
- Issue date Feb 4, 2025
- SK hynix Inc.
- Choung Ki Song
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device, memory system, and operation method of memory device
- Patent number 12,211,581
- Issue date Jan 28, 2025
- Samsung Electronics Co., Ltd.
- Donghun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear polar material based flip-flop
- Patent number 12,212,321
- Issue date Jan 28, 2025
- Kepler Computing Inc.
- Amrita Mathuriya
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method of operating same
- Patent number 12,205,664
- Issue date Jan 21, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hua-Hsin Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory and operation method thereof
- Patent number 12,190,982
- Issue date Jan 7, 2025
- SK Hynix Inc.
- Seung Chan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method of operating the same
- Patent number 12,183,428
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-cell architecture based in-memory compute
- Patent number 12,183,424
- Issue date Dec 31, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable memory timing
- Patent number 12,176,061
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling power management operations in...
- Patent number 12,165,739
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device for performing data alignment operation
- Patent number 12,154,653
- Issue date Nov 26, 2024
- SK hynix Inc.
- Young Mok Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal sampling circuit and semiconductor memory device
- Patent number 12,148,461
- Issue date Nov 19, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY AND OPERATION METHOD THEREOF
- Publication number 20250095769
- Publication date Mar 20, 2025
- SK HYNIX INC.
- Seung Chan KIM
- G11 - INFORMATION STORAGE
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING-IN-MEMORY DEVICES HAVING MULTIPLICATION-AND-ACCUMULATION...
- Publication number 20250094128
- Publication date Mar 20, 2025
- SK HYNIX INC.
- Choung Ki SONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20250078883
- Publication date Mar 6, 2025
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Controlling Power Management Operations in...
- Publication number 20250061929
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION
- Publication number 20250046352
- Publication date Feb 6, 2025
- SK HYNIX INC.
- Young Mok JEONG
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SEN...
- Publication number 20250037747
- Publication date Jan 30, 2025
- Lodestar Licensing Group, LLC
- Troy A. Manning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
- Publication number 20250029641
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEAKAGE COMPENSATED DYNAMIC LATCH
- Publication number 20250006234
- Publication date Jan 2, 2025
- Intel Corporation
- Ganesan Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA...
- Publication number 20240412792
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY
- Publication number 20240395292
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Jeffrey E. KWAK
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS
- Publication number 20240395296
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS
- Publication number 20240355378
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Akira Yamashita
- G11 - INFORMATION STORAGE
Information Patent Application
PULSE BASED MULTI-LEVEL CELL PROGRAMMING
- Publication number 20240347081
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20240321326
- Publication date Sep 26, 2024
- KIOXIA Corporation
- Koji TABATA
- G11 - INFORMATION STORAGE
Information Patent Application
SAMPLING SIGNALS
- Publication number 20240313748
- Publication date Sep 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Omer QADIR
- G11 - INFORMATION STORAGE
Information Patent Application
DIE LOCATION DETECTION FOR GROUPED MEMORY DIES
- Publication number 20240312499
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Hyunyoo Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20240312496
- Publication date Sep 19, 2024
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
- Publication number 20240289047
- Publication date Aug 29, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING THE SAME
- Publication number 20240274174
- Publication date Aug 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xiu-Li YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
- Publication number 20240274167
- Publication date Aug 15, 2024
- SK HYNIX INC.
- Hyung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE
- Publication number 20240265953
- Publication date Aug 8, 2024
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE

Data input latches

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus for multi-banked victim cache with dual datapath

Memory core characteristic screening method and system thereof

Semiconductor device including internal transmission path and stack...

Multiplication-and-accumulation circuits and processing-in-memory d...

Folding ordering scheme for improved throughput in non-volatile memory

Data receiving circuit, data receiving system and memory device

Memory system including an interface circuit connecting a controlle...

Acceleration of in-memory-compute arrays

Memory component with input/output data rate alignment

Memory component having internal read-modify-write operation

Storage device and operating method with multiple channels

Processing-in-memory devices having multiplication-and-accumulation...

Atomic compare and swap in a coherent cache system

Memory device, memory system, and operation method of memory device

Aggressive write flush scheme for a victim cache

Non-linear polar material based flip-flop

Memory circuit and method of operating same

Methods and apparatus to reduce bank pressure using aggressive writ...

Fully pipelined read-modify-write support

Memory and operation method thereof

Integrated circuit having test circuitry for memory sub-systems

Shared decoder circuit and method

Memory circuit and method of operating the same

Methods and apparatus for allocation in a victim cache system

Bit-cell architecture based in-memory compute

Programmable memory timing

Systems and methods for controlling power management operations in...

Semiconductor device for performing data alignment operation

Signal sampling circuit and semiconductor memory device

Methods and apparatus for read-modify-write support in multi-banked...

Patents Applicationslast 30 patents

MEMORY AND OPERATION METHOD THEREOF

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

PROCESSING-IN-MEMORY DEVICES HAVING MULTIPLICATION-AND-ACCUMULATION...

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

Systems and Methods for Controlling Power Management Operations in...

SEMICONDUCTOR DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SEN...

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

LEAKAGE COMPENSATED DYNAMIC LATCH

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA...

STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY

SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS

PULSE BASED MULTI-LEVEL CELL PROGRAMMING

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

SEMICONDUCTOR MEMORY DEVICE

SAMPLING SIGNALS

DIE LOCATION DETECTION FOR GROUPED MEMORY DIES

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

VICTIM CACHE WITH WRITE MISS MERGING

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE

AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE