Data input latches

Industry

CPC
G11C7/1087

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1087Data input latches

Industries

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory and operation method thereof
- Patent number 12,190,982
- Issue date Jan 7, 2025
- SK Hynix Inc.
- Seung Chan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method of operating the same
- Patent number 12,183,428
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-cell architecture based in-memory compute
- Patent number 12,183,424
- Issue date Dec 31, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable memory timing
- Patent number 12,176,061
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling power management operations in...
- Patent number 12,165,739
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device for performing data alignment operation
- Patent number 12,154,653
- Issue date Nov 26, 2024
- SK hynix Inc.
- Young Mok Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal sampling circuit and semiconductor memory device
- Patent number 12,148,461
- Issue date Nov 19, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for multiple read operations
- Patent number 12,142,343
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for performing logical operations using sen...
- Patent number 12,142,347
- Issue date Nov 12, 2024
- Troy A. Manning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calibrating write timing in a memory system
- Patent number 12,136,452
- Issue date Nov 5, 2024
- RAMBUS INC.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage system and method for improving read latency during mixed r...
- Patent number 12,136,462
- Issue date Nov 5, 2024
- SanDisk Technologies, Inc.
- Sergey Anatolievich Gorobets
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module with reduced read/write turnaround overhead
- Patent number 12,130,757
- Issue date Oct 29, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repairable latch array
- Patent number 12,100,464
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Joel Thornton Irby
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device based on daisy chain topology
- Patent number 12,087,390
- Issue date Sep 10, 2024
- SK Hynix Inc.
- Jeffrey E. Kwak
- G11 - INFORMATION STORAGE
Information Patent Grant
Flip-flop circuitry
- Patent number 12,078,679
- Issue date Sep 3, 2024
- Samsung Electronics Co., Ltd.
- Byoung Gon Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Simplified operations to read memory cells coarsely programmed via...
- Patent number 12,073,892
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device deserializer circuit with a reduced form factor
- Patent number 12,073,918
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Guan Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus, system and method to sense a logic state of a memory cel...
- Patent number 12,062,410
- Issue date Aug 13, 2024
- Intel Corporation
- Ashraf B. Islam
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip select, command, and address encoding
- Patent number 12,057,189
- Issue date Aug 6, 2024
- SanDisk Technologies LLC
- Tianyu Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular memory architecture with gated sub-array operation dependen...
- Patent number 12,046,324
- Issue date Jul 23, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LEAKAGE COMPENSATED DYNAMIC LATCH
- Publication number 20250006234
- Publication date Jan 2, 2025
- Intel Corporation
- Ganesan Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA...
- Publication number 20240412792
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY
- Publication number 20240395292
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Jeffrey E. KWAK
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS
- Publication number 20240395296
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS
- Publication number 20240355378
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Akira Yamashita
- G11 - INFORMATION STORAGE
Information Patent Application
PULSE BASED MULTI-LEVEL CELL PROGRAMMING
- Publication number 20240347081
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20240321326
- Publication date Sep 26, 2024
- KIOXIA Corporation
- Koji TABATA
- G11 - INFORMATION STORAGE
Information Patent Application
SAMPLING SIGNALS
- Publication number 20240313748
- Publication date Sep 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Omer QADIR
- G11 - INFORMATION STORAGE
Information Patent Application
DIE LOCATION DETECTION FOR GROUPED MEMORY DIES
- Publication number 20240312499
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Hyunyoo Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20240312496
- Publication date Sep 19, 2024
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
- Publication number 20240289047
- Publication date Aug 29, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING THE SAME
- Publication number 20240274174
- Publication date Aug 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xiu-Li YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
- Publication number 20240274167
- Publication date Aug 15, 2024
- SK HYNIX INC.
- Hyung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE
- Publication number 20240265953
- Publication date Aug 8, 2024
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ/WRITE SWITCHING CIRCUIT AND MEMORY
- Publication number 20240256174
- Publication date Aug 1, 2024
- Changxin Memory Technologies, Inc.
- WeiBing SHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSE DELAY OF A COMMAND IN A MEMORY PACKAGE
- Publication number 20240233791
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Christopher G. Wieduwilt
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING PAGE BUFFER CIRCUITS IN MEMORY DEVICES
- Publication number 20240233783
- Publication date Jul 11, 2024
- Macronix International Co., Ltd.
- Ji-Yu Hung
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SI...
- Publication number 20240221800
- Publication date Jul 4, 2024
- Lodestar Licensing Group LLC
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE AND DISPLAY
- Publication number 20240221801
- Publication date Jul 4, 2024
- Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Yamei BAI
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDING ORDERING SCHEME FOR IMPROVED THROUGHPUT IN NON-VOLATILE MEMORY
- Publication number 20240221802
- Publication date Jul 4, 2024
- Western Digital Technologies, Inc.
- Abhinandan Venugopal
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CORE CHARACTERISTIC SCREENING METHOD AND SYSTEM THEREOF
- Publication number 20240212728
- Publication date Jun 27, 2024
- Integrated Silicon Solution Inc.
- Jeong Ho BANG
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...
- Publication number 20240194232
- Publication date Jun 13, 2024
- SK HYNIX INC.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM
- Publication number 20240185902
- Publication date Jun 6, 2024
- SK HYNIX INC.
- Kang Sub KWAK
- G11 - INFORMATION STORAGE

Data input latches

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus to reduce bank pressure using aggressive writ...

Fully pipelined read-modify-write support

Memory and operation method thereof

Integrated circuit having test circuitry for memory sub-systems

Shared decoder circuit and method

Memory circuit and method of operating the same

Methods and apparatus for allocation in a victim cache system

Bit-cell architecture based in-memory compute

Programmable memory timing

Systems and methods for controlling power management operations in...

Semiconductor device for performing data alignment operation

Signal sampling circuit and semiconductor memory device

Methods and apparatus for read-modify-write support in multi-banked...

Memory devices for multiple read operations

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Apparatuses and methods for performing logical operations using sen...

Method and apparatus for calibrating write timing in a memory system

Storage system and method for improving read latency during mixed r...

Memory module with reduced read/write turnaround overhead

Methods and apparatus for eviction in dual datapath victim cache sy...

Repairable latch array

Storage device based on daisy chain topology

Flip-flop circuitry

Simplified operations to read memory cells coarsely programmed via...

Methods and apparatus to facilitate read-modify-write support in a...

Memory device deserializer circuit with a reduced form factor

Apparatus, system and method to sense a logic state of a memory cel...

Chip select, command, and address encoding

Modular memory architecture with gated sub-array operation dependen...

Patents Applicationslast 30 patents

LEAKAGE COMPENSATED DYNAMIC LATCH

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA...

STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY

SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS

PULSE BASED MULTI-LEVEL CELL PROGRAMMING

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

SEMICONDUCTOR MEMORY DEVICE

SAMPLING SIGNALS

DIE LOCATION DETECTION FOR GROUPED MEMORY DIES

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

VICTIM CACHE WITH WRITE MISS MERGING

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE

AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

READ/WRITE SWITCHING CIRCUIT AND MEMORY

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

FUSE DELAY OF A COMMAND IN A MEMORY PACKAGE

MANAGING PAGE BUFFER CIRCUITS IN MEMORY DEVICES

APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SI...

STORAGE DEVICE AND DISPLAY

FOLDING ORDERING SCHEME FOR IMPROVED THROUGHPUT IN NON-VOLATILE MEMORY

MEMORY CORE CHARACTERISTIC SCREENING METHOD AND SYSTEM THEREOF

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...

SEMICONDUCTOR SYSTEM