Delay testing

Industry

CPC
G01R31/31858

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31858Delay testing

Industries

Patents Grantslast 30 patents

Information Patent Grant
Reconfigurable JTAG architecture for implementation of programmable...
- Patent number 12,123,912
- Issue date Oct 22, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Grant
Protection of the content of a fuse memory
- Patent number 12,117,487
- Issue date Oct 15, 2024
- STMicroelectronics (Grenoble 2) SAS
- Mark Trimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost-saving scheme for scan testing of 3D stack die
- Patent number 12,099,091
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Songgan Zang
- G01 - MEASURING TESTING
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 12,099,090
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to identify faults in processors
- Patent number 12,085,610
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for scan chain in a memory
- Patent number 11,971,448
- Issue date Apr 30, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Invisible scan architecture for secure testing of digital designs
- Patent number 11,953,548
- Issue date Apr 9, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test-point flop sharing with improved testability in a circuit design
- Patent number 11,947,887
- Issue date Apr 2, 2024
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secured scan access for a device including a scan chain
- Patent number 11,927,633
- Issue date Mar 12, 2024
- Texas Instruments Incorporated
- Mudasir Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Using scan chains to read out data from integrated sensors during s...
- Patent number 11,921,160
- Issue date Mar 5, 2024
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Grant
Core and interface scan testing architecture and methodology
- Patent number 11,879,942
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Banadappa Shivaray
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit, test assembly and method for testing an integra...
- Patent number 11,874,325
- Issue date Jan 16, 2024
- Infineon Technologies AG
- Tobias Kilian
- G01 - MEASURING TESTING
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 11,821,947
- Issue date Nov 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,768,726
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing scan data transfer inside multi-die package with SERDES...
- Patent number 11,762,017
- Issue date Sep 19, 2023
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing artificial intelligence chip, devi...
- Patent number 11,714,128
- Issue date Aug 1, 2023
- KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
- Ziyu Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reformatting scan patterns in presence of hold type pipelines
- Patent number 11,694,010
- Issue date Jul 4, 2023
- Synopsys, Inc.
- Amit Gopal M. Purohit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using embedded time-varying code generator to provide secure access...
- Patent number 11,693,052
- Issue date Jul 4, 2023
- Silicon Aid Solutions, Inc.
- James M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-readable recording medium storing analysis program, analys...
- Patent number 11,693,054
- Issue date Jul 4, 2023
- Fujitsu Limited
- Daisuke Maruyama
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain for memory with reduced power consumption
- Patent number 11,693,056
- Issue date Jul 4, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- G01 - MEASURING TESTING
Information Patent Grant
Chip, chip testing method and electronic device
- Patent number 11,686,771
- Issue date Jun 27, 2023
- CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
- Yuqian Cedric Wong
- G01 - MEASURING TESTING
Information Patent Grant
Input data compression for machine learning-based chain diagnosis
- Patent number 11,681,843
- Issue date Jun 20, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC device authentication using energy characterization
- Patent number 11,630,150
- Issue date Apr 18, 2023
- Science Applications International Corporation
- David Michael Barrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core partition circuit and testing device
- Patent number 11,624,782
- Issue date Apr 11, 2023
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Yunhao Xing
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed flipflop circuit
- Patent number 11,545,964
- Issue date Jan 3, 2023
- Samsung Electronics Co., Ltd.
- Wonhyun Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling test networks of chips using integrated processors
- Patent number 11,526,644
- Issue date Dec 13, 2022
- NVIDIA Corporation
- Kaushik Narayanun
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT
- Publication number 20240402246
- Publication date Dec 5, 2024
- International Business Machines Corporation
- BENJAMIN NEIL TROMBLEY
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20240369629
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS
- Publication number 20240345160
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUES FOR INFIELD TESTING OF CRYPTOGRAPHIC CIRCUITRY
- Publication number 20240264231
- Publication date Aug 8, 2024
- Intel Corporation
- Rakesh KANDULA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN
- Publication number 20240241174
- Publication date Jul 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mudasir KAWOOSA
- G01 - MEASURING TESTING
Information Patent Application
SCAN FLIP-FLOP, SCAN CHAIN CIRCUIT INCLUDING THE SAME, AND CONTROL...
- Publication number 20240142521
- Publication date May 2, 2024
- Research & Business Foundation Sungkyunkwan University
- Changyoun Im
- G01 - MEASURING TESTING
Information Patent Application
Techniques For Storing States Of Signals In Configurable Storage Ci...
- Publication number 20240137026
- Publication date Apr 25, 2024
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20240027525
- Publication date Jan 25, 2024
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE
- Publication number 20240019493
- Publication date Jan 18, 2024
- ADVANCED MICRO DEVICES, INC.
- SongGan Zang
- G01 - MEASURING TESTING
Information Patent Application
PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS...
- Publication number 20240003973
- Publication date Jan 4, 2024
- Intel Corporation
- Ratheesh Thekke Veetil
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20230408582
- Publication date Dec 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process for Scan Chain in a Memory
- Publication number 20230296672
- Publication date Sep 21, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Scan Chain for Memory with Reduced Power Consumption
- Publication number 20230194607
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Shakti SINGH
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE JTAG ARCHITECTURE FOR IMPLEMENTATION OF PROGRAMMABLE...
- Publication number 20220357394
- Publication date Nov 10, 2022
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Application
Using Embedded Time-Varying Code Generator to Provide Secure Access...
- Publication number 20220244311
- Publication date Aug 4, 2022
- SiliconAid Solutions, Inc.
- James M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20220091919
- Publication date Mar 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20220082623
- Publication date Mar 17, 2022
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS
- Publication number 20220065932
- Publication date Mar 3, 2022
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
IC Device Authentication Using Energy Characterization
- Publication number 20210311113
- Publication date Oct 7, 2021
- Science Applications International Corporation
- David Michael Barrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED FLIPFLOP CIRCUIT
- Publication number 20210270899
- Publication date Sep 2, 2021
- Samsung Electronics Co., Ltd.
- Wonhyun Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20210239759
- Publication date Aug 5, 2021
- KIOXIA Corporation
- Masaki OOISO
- G01 - MEASURING TESTING
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20210116503
- Publication date Apr 22, 2021
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20210088584
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-AWARE SCAN PARTITIONING
- Publication number 20200311329
- Publication date Oct 1, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE, METHOD FOR DIAGNOSING SEMICONDUCTOR DEVICE, A...
- Publication number 20200300915
- Publication date Sep 24, 2020
- Kabushiki Kaisha Toshiba
- Tomohiro TACHIKAWA
- G01 - MEASURING TESTING
Information Patent Application
IC Device Authentication Using Energy Characterization
- Publication number 20200271719
- Publication date Aug 27, 2020
- SAIC
- David Michael Barrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT APPLIED TO MULTIPLE SCAN MODES FOR TESTING
- Publication number 20200182933
- Publication date Jun 11, 2020
- Realtek Semiconductor Corp.
- Tzung-Jin Wu
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR MICROWAVE MIXER PHASE RESPONSE MEASUREMENT
- Publication number 20200166565
- Publication date May 28, 2020
- Fermi Research Alliance, LLC
- Daniil Frolov
- G01 - MEASURING TESTING

Delay testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Reconfigurable JTAG architecture for implementation of programmable...

Protection of the content of a fuse memory

Cost-saving scheme for scan testing of 3D stack die

Multiplexer for SDFQ having differently-sized scan and data transis...

Methods and apparatus to identify faults in processors

Systems and methods for scan chain stitching

Process for scan chain in a memory

Invisible scan architecture for secure testing of digital designs

Test-point flop sharing with improved testability in a circuit design

Secured scan access for a device including a scan chain

Using scan chains to read out data from integrated sensors during s...

Core and interface scan testing architecture and methodology

Integrated circuit, test assembly and method for testing an integra...

Multiplexer for SDFQ having differently-sized scan and data transis...

Wafer scale testing using a 2 signal JTAG interface

Delay fault testing of pseudo static controls

Performing scan data transfer inside multi-die package with SERDES...

Method and apparatus for testing artificial intelligence chip, devi...

Reformatting scan patterns in presence of hold type pipelines

Using embedded time-varying code generator to provide secure access...

Computer-readable recording medium storing analysis program, analys...

Scan chain for memory with reduced power consumption

Chip, chip testing method and electronic device

Input data compression for machine learning-based chain diagnosis

IC device authentication using energy characterization

Core partition circuit and testing device

Trajectory-optimized test pattern generation for built-in self-test

Wafer scale testing using a 2 signal JTAG interface

High speed flipflop circuit

Controlling test networks of chips using integrated processors

Patents Applicationslast 30 patents

ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

TECHNIQUES FOR INFIELD TESTING OF CRYPTOGRAPHIC CIRCUITRY

SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN

SCAN FLIP-FLOP, SCAN CHAIN CIRCUIT INCLUDING THE SAME, AND CONTROL...

Techniques For Storing States Of Signals In Configurable Storage Ci...

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE

PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS...

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

Process for Scan Chain in a Memory

Scan Chain for Memory with Reduced Power Consumption

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

RECONFIGURABLE JTAG ARCHITECTURE FOR IMPLEMENTATION OF PROGRAMMABLE...

Using Embedded Time-Varying Code Generator to Provide Secure Access...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS

IC Device Authentication Using Energy Characterization

HIGH SPEED FLIPFLOP CIRCUIT

SEMICONDUCTOR INTEGRATED CIRCUIT

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

POWER-AWARE SCAN PARTITIONING

SEMICONDUCTOR DEVICE, METHOD FOR DIAGNOSING SEMICONDUCTOR DEVICE, A...

IC Device Authentication Using Energy Characterization

CIRCUIT APPLIED TO MULTIPLE SCAN MODES FOR TESTING

METHOD AND SYSTEM FOR MICROWAVE MIXER PHASE RESPONSE MEASUREMENT