Design for test

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CPC
G01R31/318583

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318583Design for test

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Error protection analysis of an integrated circuit
- Patent number 12,188,979
- Issue date Jan 7, 2025
- International Business Machines Corporation
- Benjamin Neil Trombley
- G01 - MEASURING TESTING
Information Patent Grant
Cost-saving scheme for scan testing of 3D stack die
- Patent number 12,099,091
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Songgan Zang
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for scan chain in a memory
- Patent number 11,971,448
- Issue date Apr 30, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test-point flop sharing with improved testability in a circuit design
- Patent number 11,947,887
- Issue date Apr 2, 2024
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit, test assembly and method for testing an integra...
- Patent number 11,874,325
- Issue date Jan 16, 2024
- Infineon Technologies AG
- Tobias Kilian
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing scan data transfer inside multi-die package with SERDES...
- Patent number 11,762,017
- Issue date Sep 19, 2023
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing artificial intelligence chip, devi...
- Patent number 11,714,128
- Issue date Aug 1, 2023
- KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
- Ziyu Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reformatting scan patterns in presence of hold type pipelines
- Patent number 11,694,010
- Issue date Jul 4, 2023
- Synopsys, Inc.
- Amit Gopal M. Purohit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain for memory with reduced power consumption
- Patent number 11,693,056
- Issue date Jul 4, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- G01 - MEASURING TESTING
Information Patent Grant
Chip, chip testing method and electronic device
- Patent number 11,686,771
- Issue date Jun 27, 2023
- CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
- Yuqian Cedric Wong
- G01 - MEASURING TESTING
Information Patent Grant
Input data compression for machine learning-based chain diagnosis
- Patent number 11,681,843
- Issue date Jun 20, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core partition circuit and testing device
- Patent number 11,624,782
- Issue date Apr 11, 2023
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Yunhao Xing
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed flipflop circuit
- Patent number 11,545,964
- Issue date Jan 3, 2023
- Samsung Electronics Co., Ltd.
- Wonhyun Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling test networks of chips using integrated processors
- Patent number 11,526,644
- Issue date Dec 13, 2022
- NVIDIA Corporation
- Kaushik Narayanun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Suspect resolution for scan chain defect diagnosis
- Patent number 11,423,202
- Issue date Aug 23, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for optimizing scan pipelining in hierarchical...
- Patent number 11,409,931
- Issue date Aug 9, 2022
- Cadence Design Systems, Inc.
- Jagjot Kaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-aware scan partitioning
- Patent number 11,386,253
- Issue date Jul 12, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage machine learning-based chain diagnosis
- Patent number 11,361,248
- Issue date Jun 14, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test method and test system
- Patent number 11,320,484
- Issue date May 3, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Shu-Liang Ning
- G01 - MEASURING TESTING
Information Patent Grant
Testing of asynchronous reset logic
- Patent number 11,301,607
- Issue date Apr 12, 2022
- NXP B.V.
- Tom Waayers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test method and test system
- Patent number 11,293,982
- Issue date Apr 5, 2022
- Rohde & Schwarz GmbH & Co. KG
- Philip Diegmann
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,243,253
- Issue date Feb 8, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failure diagnostic apparatus and failure diagnostic method
- Patent number 11,193,974
- Issue date Dec 7, 2021
- Renesas Electronics Corporation
- Yukihisa Funatsu
- G01 - MEASURING TESTING
Information Patent Grant
Performing scan data transfer inside multi-die package with SERDES...
- Patent number 11,181,579
- Issue date Nov 23, 2021
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit having multiple scan modes for testing
- Patent number 11,073,558
- Issue date Jul 27, 2021
- Realtek Semiconductor Corp.
- Tzung-Jin Wu
- G01 - MEASURING TESTING
Information Patent Grant
Double edge triggered Mux-D scan flip-flop
- Patent number 11,054,470
- Issue date Jul 6, 2021
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT
- Publication number 20240402246
- Publication date Dec 5, 2024
- International Business Machines Corporation
- BENJAMIN NEIL TROMBLEY
- G01 - MEASURING TESTING
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20240027525
- Publication date Jan 25, 2024
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE
- Publication number 20240019493
- Publication date Jan 18, 2024
- ADVANCED MICRO DEVICES, INC.
- SongGan Zang
- G01 - MEASURING TESTING
Information Patent Application
Process for Scan Chain in a Memory
- Publication number 20230296672
- Publication date Sep 21, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Scan Chain for Memory with Reduced Power Consumption
- Publication number 20230194607
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Shakti SINGH
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20220082623
- Publication date Mar 17, 2022
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS
- Publication number 20220065932
- Publication date Mar 3, 2022
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
HIGH SPEED FLIPFLOP CIRCUIT
- Publication number 20210270899
- Publication date Sep 2, 2021
- Samsung Electronics Co., Ltd.
- Wonhyun Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...
- Publication number 20210116503
- Publication date Apr 22, 2021
- ADVANCED MICRO DEVICES, INC.
- AHMET TOKUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20210088584
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-AWARE SCAN PARTITIONING
- Publication number 20200311329
- Publication date Oct 1, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE, METHOD FOR DIAGNOSING SEMICONDUCTOR DEVICE, A...
- Publication number 20200300915
- Publication date Sep 24, 2020
- Kabushiki Kaisha Toshiba
- Tomohiro TACHIKAWA
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT APPLIED TO MULTIPLE SCAN MODES FOR TESTING
- Publication number 20200182933
- Publication date Jun 11, 2020
- Realtek Semiconductor Corp.
- Tzung-Jin Wu
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20200124667
- Publication date Apr 23, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test Generation Using Testability-Based Guidance
- Publication number 20190293718
- Publication date Sep 26, 2019
- Mentor Graphics Corporation
- Sylwester Milewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20190120899
- Publication date Apr 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
POWER-AWARE SCAN PARTITIONING
- Publication number 20190094303
- Publication date Mar 28, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY
- Publication number 20190056450
- Publication date Feb 21, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY
- Publication number 20190056449
- Publication date Feb 21, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20180321307
- Publication date Nov 8, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20180128875
- Publication date May 10, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Mixed-Signal Integrated Circuit
- Publication number 20180003770
- Publication date Jan 4, 2018
- Huawei Technologies Co., Ltd
- Udi Nir
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology
- Publication number 20140372819
- Publication date Dec 18, 2014
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SCAN CHAIN RE-ORDERING
- Publication number 20140223249
- Publication date Aug 7, 2014
- Puneet Dodeja
- G01 - MEASURING TESTING
Information Patent Application
Multiple-Capture DFT System for Detecting or Locating Crossing Cloc...
- Publication number 20140223251
- Publication date Aug 7, 2014
- Syntest Technologies, Inc.
- Laung-Terng Wang
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHI...
- Publication number 20140091812
- Publication date Apr 3, 2014
- Realtek Semiconductor Corp.
- Ming-Chung Wu
- G01 - MEASURING TESTING
Information Patent Application
Multiple-Capture DFT System for Detecting or Locating Crossing Cloc...
- Publication number 20140082446
- Publication date Mar 20, 2014
- Syntest Technologies, Inc.
- Laung-Terng Wang
- G01 - MEASURING TESTING
Information Patent Application
Computer-Aided Design (CAD) Multiple-Capture DFT System for Detecti...
- Publication number 20140075257
- Publication date Mar 13, 2014
- Syntest Technologies, Inc.
- Laung-Terng Wang
- G01 - MEASURING TESTING

Design for test

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Error protection analysis of an integrated circuit

Cost-saving scheme for scan testing of 3D stack die

Systems and methods for scan chain stitching

Process for scan chain in a memory

Test-point flop sharing with improved testability in a circuit design

Integrated circuit, test assembly and method for testing an integra...

Wafer scale testing using a 2 signal JTAG interface

Performing scan data transfer inside multi-die package with SERDES...

Method and apparatus for testing artificial intelligence chip, devi...

Reformatting scan patterns in presence of hold type pipelines

Scan chain for memory with reduced power consumption

Chip, chip testing method and electronic device

Input data compression for machine learning-based chain diagnosis

Core partition circuit and testing device

Trajectory-optimized test pattern generation for built-in self-test

Wafer scale testing using a 2 signal JTAG interface

High speed flipflop circuit

Controlling test networks of chips using integrated processors

Suspect resolution for scan chain defect diagnosis

Systems and methods for optimizing scan pipelining in hierarchical...

Power-aware scan partitioning

Multi-stage machine learning-based chain diagnosis

Test method and test system

Testing of asynchronous reset logic

Test method and test system

Wafer scale testing using a 2 signal JTAG interface

Failure diagnostic apparatus and failure diagnostic method

Performing scan data transfer inside multi-die package with SERDES...

Circuit having multiple scan modes for testing

Double edge triggered Mux-D scan flip-flop

Patents Applicationslast 30 patents

ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE

Process for Scan Chain in a Memory

Scan Chain for Memory with Reduced Power Consumption

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS

HIGH SPEED FLIPFLOP CIRCUIT

PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

POWER-AWARE SCAN PARTITIONING

SEMICONDUCTOR DEVICE, METHOD FOR DIAGNOSING SEMICONDUCTOR DEVICE, A...

CIRCUIT APPLIED TO MULTIPLE SCAN MODES FOR TESTING

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

Test Generation Using Testability-Based Guidance

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

POWER-AWARE SCAN PARTITIONING

CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY

CIRCUIT STRUCTURES TO RESOLVE RANDOM TESTABILITY

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

Mixed-Signal Integrated Circuit

Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology

SYSTEM AND METHOD FOR SCAN CHAIN RE-ORDERING

Multiple-Capture DFT System for Detecting or Locating Crossing Cloc...

METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHI...

Multiple-Capture DFT System for Detecting or Locating Crossing Cloc...

Computer-Aided Design (CAD) Multiple-Capture DFT System for Detecti...