Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces

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H01L2224/81894

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/81894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method of room temperature covalent bonding
- Patent number 11,760,059
- Issue date Sep 19, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Qin-Yi Tong
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
3D IC method and device
- Patent number 11,515,202
- Issue date Nov 29, 2022
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC method and device
- Patent number 11,289,372
- Issue date Mar 29, 2022
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 11,205,602
- Issue date Dec 21, 2021
- Amkor Technology Singapore Holding Pte Ltd.
- Jin Young Khim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC method and device
- Patent number 11,011,418
- Issue date May 18, 2021
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures with extended conductive pathways
- Patent number 10,872,834
- Issue date Dec 22, 2020
- Intel Corporation
- Yen Hsiang Chew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optoelectronic component and method for producing an optoelectronic...
- Patent number 10,686,099
- Issue date Jun 16, 2020
- OSRAM OLED GmbH
- Sophia Huppmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of room temperature covalent bonding
- Patent number 10,434,749
- Issue date Oct 8, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Qin-Yi Tong
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Three dimensional device integration method and integrated device
- Patent number 10,366,962
- Issue date Jul 30, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Tooling for coupling multiple electronic chips
- Patent number 10,340,239
- Issue date Jul 2, 2019
- Cufer Asset Ltd. L.L.C.
- Roger Dugas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC method and device
- Patent number 10,147,641
- Issue date Dec 4, 2018
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Room temperature metal direct bonding
- Patent number 10,141,218
- Issue date Nov 27, 2018
- INVENSAS BONDING TECHNOLOGIES, INC.
- Qin-Yi Tong
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Tooling for coupling multiple electronic chips
- Patent number 9,754,907
- Issue date Sep 5, 2017
- Cufer Asset Ltd. L.L.C.
- Roger Dugas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC method and device
- Patent number 9,716,033
- Issue date Jul 25, 2017
- ZIPTRONIX, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming 3-D circuits with integrated passive devices
- Patent number 9,698,131
- Issue date Jul 4, 2017
- Invensas Corporation
- Paul W. Sanders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for aligning micro-electronic components
- Patent number 9,601,459
- Issue date Mar 21, 2017
- Imec VZW
- Vikas Dubey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional device integration method and integrated device
- Patent number 9,564,414
- Issue date Feb 7, 2017
- ZIPTRONIX, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional device integration method and integrated device
- Patent number 9,431,368
- Issue date Aug 30, 2016
- Ziptronix, Inc.
- Paul M. Enquist
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Apparatus and method of substrate to substrate bonding for three di...
- Patent number 9,418,961
- Issue date Aug 16, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Room temperature metal direct bonding
- Patent number 9,385,024
- Issue date Jul 5, 2016
- Ziptronix, Inc.
- Qin-Yi Tong
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Tooling for coupling multiple electronic chips
- Patent number 9,324,629
- Issue date Apr 26, 2016
- Cufer Asset Ltd. L.L.C.
- Roger Dugas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally enhanced wafer level fan-out POP package
- Patent number 9,318,474
- Issue date Apr 19, 2016
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming 3-D circuits with integrated passive devices
- Patent number 9,236,365
- Issue date Jan 12, 2016
- Invensas Corporation
- Paul W. Sanders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC method and device
- Patent number 9,171,756
- Issue date Oct 27, 2015
- Ziptronix, Inc.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact-based encapsulation
- Patent number 9,147,635
- Issue date Sep 29, 2015
- Cufer Asset Ltd. L.L.C.
- John Trezza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC method and device
- Patent number 9,130,021
- Issue date Sep 8, 2015
- Ziptronix, Inc.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of handling a thin wafer
- Patent number 9,117,828
- Issue date Aug 25, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Weng-Jin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for direct bonding two elements comprising copper portions...
- Patent number 9,027,821
- Issue date May 12, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Lea Di Cioccio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Through hole vias at saw streets including protrusions or recesses...
- Patent number 8,940,636
- Issue date Jan 27, 2015
- STATS ChipPAC, Ltc.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and production method therefor
- Patent number 8,927,341
- Issue date Jan 6, 2015
- Nichia Corporation
- Masafumi Kuramoto
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D IC METHOD AND DEVICE
- Publication number 20210313225
- Publication date Oct 7, 2021
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D IC METHOD AND DEVICE
- Publication number 20210280461
- Publication date Sep 9, 2021
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSCEIVER DIE INTERCONNECT INTERFACES
- Publication number 20200273824
- Publication date Aug 27, 2020
- Intel Corporation
- Telesphor Kamgaing
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH EXTENDED CONDUCTIVE PATHWAYS
- Publication number 20200135603
- Publication date Apr 30, 2020
- Intel Corporation
- YEN HSIANG CHEW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ROOM TEMPERATURE COVALENT BONDING
- Publication number 20190344534
- Publication date Nov 14, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Qin-Yi Tong
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF ROOM TEMPERATURE COVALENT BONDING
- Publication number 20190344533
- Publication date Nov 14, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Qin-Yi Tong
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
3D IC METHOD AND DEVICE
- Publication number 20190148222
- Publication date May 16, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROOM TEMPERATURE METAL DIRECT BONDING
- Publication number 20190115247
- Publication date Apr 18, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Qin-Yi Tong
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS
- Publication number 20180033754
- Publication date Feb 1, 2018
- Cufer Asset Ltd. L.L.C.
- Roger Dugas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D IC METHOD AND DEVICE
- Publication number 20170316971
- Publication date Nov 2, 2017
- ZIPTRONIX, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS
- Publication number 20160322320
- Publication date Nov 3, 2016
- Cufer Asset Ltd. L.L.C.
- Roger Dugas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermally Enhanced Wafer Level Fan-Out POP Package
- Publication number 20150171063
- Publication date Jun 18, 2015
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
- Publication number 20150061101
- Publication date Mar 5, 2015
- United Test & Assembly Center Ltd.
- Kriangsak Sae LE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HERMETICALLY-SEALED ELECTRICAL CIRCUIT APPARATUS
- Publication number 20140374145
- Publication date Dec 25, 2014
- Paul F. Gerrish
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROOM TEMPERATURE METAL DIRECT BONDING
- Publication number 20140370658
- Publication date Dec 18, 2014
- Ziptronix, Inc.
- Qin-Yi Tong
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES
- Publication number 20140332980
- Publication date Nov 13, 2014
- Invensas Corporation
- Paul W. Sanders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D IC METHOD AND DEVICE
- Publication number 20140187040
- Publication date Jul 3, 2014
- Ziptronix, Inc.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
- Publication number 20140141550
- Publication date May 22, 2014
- Nichia Corporation.
- Masafumi KURAMOTO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Packages, Methods of Forming Integrated Circuit...
- Publication number 20130330882
- Publication date Dec 12, 2013
- Micron Technology, Inc.
- Setho Sing Fee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and Method of Substrate to Substrate Bonding for Three Di...
- Publication number 20130320071
- Publication date Dec 5, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
PROCESS FOR DIRECT BONDING TWO ELEMENTS COMPRISING COPPER PORTIONS...
- Publication number 20130270328
- Publication date Oct 17, 2013
- COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
- Lea Di Cioccio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROOM TEMPERATURE METAL DIRECT BONDING
- Publication number 20130233473
- Publication date Sep 12, 2013
- Ziptronix, Inc.
- Qin-Yi Tong
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
3D IC METHOD AND DEVICE
- Publication number 20130178062
- Publication date Jul 11, 2013
- Ziptronix, Inc.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES
- Publication number 20130143367
- Publication date Jun 6, 2013
- FREESCALE SEMICONDUCTOR, INC.
- PAUL W. SANDERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR WAFER LEVEL PACKAGING OF ELECTRONIC DEVICES
- Publication number 20120322206
- Publication date Dec 20, 2012
- SKYWORKS SOLUTIONS, INC.
- Behnam Tabrizi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
APPARATUS FOR RESTRICTING MOISTURE INGRESS
- Publication number 20120311855
- Publication date Dec 13, 2012
- Medtronic, Inc.
- Tyler Mueller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING SAME
- Publication number 20120313237
- Publication date Dec 13, 2012
- SOITEC
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS
- Publication number 20120280387
- Publication date Nov 8, 2012
- Shriram Ramanathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ROOM TEMPERATURE COVALENT BONDING
- Publication number 20120183808
- Publication date Jul 19, 2012
- Ziptronix, Inc.
- Qin-Yi Tong
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
- Publication number 20120153486
- Publication date Jun 21, 2012
- Nichia Corporation.
- Masafumi KURAMOTO
- H01 - BASIC ELECTRIC ELEMENTS

Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of room temperature covalent bonding

3D IC method and device

3D IC method and device

Semiconductor device and manufacturing method thereof

3D IC method and device

Integrated circuit structures with extended conductive pathways

Optoelectronic component and method for producing an optoelectronic...

Method of room temperature covalent bonding

Three dimensional device integration method and integrated device

Tooling for coupling multiple electronic chips

3D IC method and device

Room temperature metal direct bonding

Tooling for coupling multiple electronic chips

3D IC method and device

Methods of forming 3-D circuits with integrated passive devices

Method for aligning micro-electronic components

Three dimensional device integration method and integrated device

Three dimensional device integration method and integrated device

Apparatus and method of substrate to substrate bonding for three di...

Room temperature metal direct bonding

Tooling for coupling multiple electronic chips

Thermally enhanced wafer level fan-out POP package

Methods of forming 3-D circuits with integrated passive devices

3D IC method and device

Contact-based encapsulation

3D IC method and device

Method of handling a thin wafer

Process for direct bonding two elements comprising copper portions...

Through hole vias at saw streets including protrusions or recesses...

Semiconductor device and production method therefor

Patents Applicationslast 30 patents

3D IC METHOD AND DEVICE

3D IC METHOD AND DEVICE

TRANSCEIVER DIE INTERCONNECT INTERFACES

INTEGRATED CIRCUIT STRUCTURES WITH EXTENDED CONDUCTIVE PATHWAYS

METHOD OF ROOM TEMPERATURE COVALENT BONDING

METHOD OF ROOM TEMPERATURE COVALENT BONDING

3D IC METHOD AND DEVICE

ROOM TEMPERATURE METAL DIRECT BONDING

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

3D IC METHOD AND DEVICE

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

Thermally Enhanced Wafer Level Fan-Out POP Package

SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

HERMETICALLY-SEALED ELECTRICAL CIRCUIT APPARATUS

ROOM TEMPERATURE METAL DIRECT BONDING

METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES

3D IC METHOD AND DEVICE

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

Integrated Circuit Packages, Methods of Forming Integrated Circuit...

Apparatus and Method of Substrate to Substrate Bonding for Three Di...

PROCESS FOR DIRECT BONDING TWO ELEMENTS COMPRISING COPPER PORTIONS...

ROOM TEMPERATURE METAL DIRECT BONDING

3D IC METHOD AND DEVICE

METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES

METHOD FOR WAFER LEVEL PACKAGING OF ELECTRONIC DEVICES

APPARATUS FOR RESTRICTING MOISTURE INGRESS

BONDED SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING SAME

THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS

METHOD OF ROOM TEMPERATURE COVALENT BONDING

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR