Etching a temporary substrate after encapsulation process to form leads

Industry

CPC
H01L21/4832

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Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Current Industry

H01L21/4832Etching a temporary substrate after encapsulation process to form leads

Industries

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 11,804,426
- Issue date Oct 31, 2023
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe package with side solder ball contact and method of manuf...
- Patent number 11,658,098
- Issue date May 23, 2023
- STMicroelectronics, Inc.
- Jefferson Talledo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with interlocking leads and manufacturing the same
- Patent number 11,557,548
- Issue date Jan 17, 2023
- STMicroelectronics, Inc.
- Aaron Cadag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating circuit components in matrix batches
- Patent number 11,521,862
- Issue date Dec 6, 2022
- Chih-liang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame, package structure and method for manufacturing the same
- Patent number 11,450,596
- Issue date Sep 20, 2022
- Advanced Semiconductor Engineering, Inc.
- Yi-Cheng Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure
- Patent number 11,417,581
- Issue date Aug 16, 2022
- PHOENIX PIONEER TECHNOLOGY CO., LTD.
- Shih-Ping Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating carrier-free semiconductor package
- Patent number 11,289,409
- Issue date Mar 29, 2022
- Siliconware Precision Industries Co., Ltd.
- Yueh-Ying Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing die package structure
- Patent number 11,264,355
- Issue date Mar 1, 2022
- COMCHIP TECHNOLOGY CO., LTD.
- Chien-Chih Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 11,107,757
- Issue date Aug 31, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for contacting a buried interconnect rail of an integrated c...
- Patent number 10,985,057
- Issue date Apr 20, 2021
- Imec VZW
- Anne Jourdain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrates for semiconductor packages
- Patent number 10,937,709
- Issue date Mar 2, 2021
- Infineon Technologies AG
- Carlo Marbella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with interlocking leads and manufacturing the same
- Patent number 10,903,172
- Issue date Jan 26, 2021
- STMicroelectronics, Inc.
- Aaron Cadag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of using leadframe bodies to form o...
- Patent number 10,903,183
- Issue date Jan 26, 2021
- JCET Semiconductor (Shaoxing) Co., Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fingerprint chip package and method for processing same
- Patent number 10,854,536
- Issue date Dec 1, 2020
- Shenzhen Goodix Technology Co., Ltd.
- Shanshan Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leadframe package with side solder ball contact and method of manuf...
- Patent number 10,840,168
- Issue date Nov 17, 2020
- STMicroelectronics, Inc.
- Jefferson Talledo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,770,333
- Issue date Sep 8, 2020
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,770,332
- Issue date Sep 8, 2020
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermosonically bonded connection for flip chip packages
- Patent number 10,741,415
- Issue date Aug 11, 2020
- STMicroelectronics S.r.l.
- Mauro Mazzola
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame
- Patent number 10,727,171
- Issue date Jul 28, 2020
- OHKUCHI MATERIALS CO., LTD.
- Kaoru Hishiki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having die pad
- Patent number 10,707,153
- Issue date Jul 7, 2020
- STMicroelectronics S.r.l.
- Federico Giovanni Ziglioli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with vertical interconnect between carrier and clip
- Patent number 10,707,158
- Issue date Jul 7, 2020
- Infineon Technologies AG
- Alexander Heinrich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,707,111
- Issue date Jul 7, 2020
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip package with resilient conductive paste post and...
- Patent number 10,685,943
- Issue date Jun 16, 2020
- Mediatek Inc.
- Shiann-Tsong Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe having organic, polymerizable photo-imageable adhesion layer
- Patent number 10,672,692
- Issue date Jun 2, 2020
- Texas Instruments Incorporated
- Jaimal Mallory Williamson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 10,672,693
- Issue date Jun 2, 2020
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Protection from ESD during the manufacturing process of semiconduct...
- Patent number 10,672,689
- Issue date Jun 2, 2020
- STMicroelectronics, Inc.
- Frederick Ray Gomez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame and method for manufacturing the same
- Patent number 10,622,286
- Issue date Apr 14, 2020
- OHKUCHI MATERIALS CO., LTD.
- Masaki Yamaguchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package having a raised lead edge
- Patent number 10,607,925
- Issue date Mar 31, 2020
- ALLEGRO MICROSYSTEMS, LLC
- Paul A. David
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming PIP with inner known goo...
- Patent number RE47923
- Issue date Mar 31, 2020
- STATS ChipPAC Pte. Ltd.
- Zigmund R. Camacho
Information Patent Grant
Carrier-free semiconductor package and fabrication method
- Patent number 10,566,271
- Issue date Feb 18, 2020
- Siliconware Precision Industries Co., Ltd.
- Yueh-Ying Tsai
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Package and Method for Fabricating a Semiconductor Pa...
- Publication number 20220037222
- Publication date Feb 3, 2022
- Khay Chwan Andrew Saw
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20210351116
- Publication date Nov 11, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING DIE PACKAGE STRUCTURE
- Publication number 20210265304
- Publication date Aug 26, 2021
- Comchip Technology Co.,Ltd.
- Chien-Chih LAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME, PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20210159155
- Publication date May 27, 2021
- Advanced Semiconductor Engineering, Inc.
- Yi-Cheng HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME
- Publication number 20210118818
- Publication date Apr 22, 2021
- STMICROELECTRONICS, INC.
- Aaron Cadag.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUF...
- Publication number 20210050282
- Publication date Feb 18, 2021
- STMICROELECTRONICS, INC.
- Jefferson TALLEDO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20200251411
- Publication date Aug 6, 2020
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATES FOR SEMICONDUCTOR PACKAGES
- Publication number 20200227330
- Publication date Jul 16, 2020
- INFINEON TECHNOLOGIES AG
- Carlo Marbella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR CONTACTING A BURIED INTERCONNECT RAIL OF AN INTEGRATED C...
- Publication number 20200152508
- Publication date May 14, 2020
- IMEC vzw
- Anne Jourdain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING CARRIER-FREE SEMICONDUCTOR PACKAGE
- Publication number 20200144167
- Publication date May 7, 2020
- Siliconware Precision Industries Co., Ltd.
- Yueh-Ying Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME
- Publication number 20200118944
- Publication date Apr 16, 2020
- STMicroelectronics, Inc.
- Aaron Cadag.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCT...
- Publication number 20190326201
- Publication date Oct 24, 2019
- STMICROELECTRONICS, INC.
- Frederick Ray GOMEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20190304887
- Publication date Oct 3, 2019
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...
- Publication number 20190198376
- Publication date Jun 27, 2019
- Semiconductor Components Industries, LLC
- Darrell D. TRUHITTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...
- Publication number 20190198375
- Publication date Jun 27, 2019
- Semiconductor Components Industries, LLC
- Darrell D. TRUHITTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...
- Publication number 20190198374
- Publication date Jun 27, 2019
- Semiconductor Components Industries, LLC
- Darrell D. TRUHITTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Package Having A Raised Lead Edge
- Publication number 20190109072
- Publication date Apr 11, 2019
- Allegro Microsystems, LLC
- Paul A. David
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMOSONICALLY BONDED CONNECTION FOR FLIP CHIP PACKAGES
- Publication number 20190088503
- Publication date Mar 21, 2019
- STMicroelectronics S.r.l.
- Mauro Mazzola
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20190088506
- Publication date Mar 21, 2019
- Advanced Semiconductor Engineering, Inc.
- Bernd Karl APPELT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUF...
- Publication number 20190074241
- Publication date Mar 7, 2019
- STMICROELECTRONICS, INC.
- Jefferson TALLEDO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME
- Publication number 20190067212
- Publication date Feb 28, 2019
- STMicroelectronics, Inc.
- Aaron Cadag.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
- Publication number 20180315678
- Publication date Nov 1, 2018
- PHOENIX PIONEER TECHNOLOGY CO., LTD.
- Shih-Ping Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
- Publication number 20180254238
- Publication date Sep 6, 2018
- Advanced Semiconductor Engineering, Inc.
- Li Chuan TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...
- Publication number 20180174881
- Publication date Jun 21, 2018
- Semiconductor Components Industries, LLC
- Darrell D. TRUHITTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME
- Publication number 20180158760
- Publication date Jun 7, 2018
- SH MATERIALS CO., LTD.
- Kaoru HISHIKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FORMING LEADFRAME HAVING ORGANIC, POLYMERIZABLE PHOTO-I...
- Publication number 20180096859
- Publication date Apr 5, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Jaimal Mallory Williamson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer
- Publication number 20180096860
- Publication date Apr 5, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Jaimal Mallory Williamson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE
- Publication number 20180076185
- Publication date Mar 15, 2018
- MEDIATEK INC.
- Shiann-Tsong Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD CARRIER WITH PRINT FORMED PACKAGE COMPONENTS AND CONDUCTIVE PA...
- Publication number 20180047589
- Publication date Feb 15, 2018
- EoPlex Limited
- Philip E ROGREN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD
- Publication number 20170200671
- Publication date Jul 13, 2017
- Siliconware Precision Industries Co., Ltd.
- Yueh-Ying Tsai
- H01 - BASIC ELECTRIC ELEMENTS

Etching a temporary substrate after encapsulation process to form leads

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Integrated circuit structures in package substrates

Leadframe package with side solder ball contact and method of manuf...

Package with interlocking leads and manufacturing the same

Process for fabricating circuit components in matrix batches

Lead frame, package structure and method for manufacturing the same

Package structure

Method for fabricating carrier-free semiconductor package

Method of manufacturing die package structure

Integrated circuit structures in package substrates

Method for contacting a buried interconnect rail of an integrated c...

Substrates for semiconductor packages

Package with interlocking leads and manufacturing the same

Semiconductor device and method of using leadframe bodies to form o...

Fingerprint chip package and method for processing same

Leadframe package with side solder ball contact and method of manuf...

Wafer level flat no-lead semiconductor packages and methods of manu...

Wafer level flat no-lead semiconductor packages and methods of manu...

Thermosonically bonded connection for flip chip packages

Lead frame

Semiconductor device having die pad

Package with vertical interconnect between carrier and clip

Wafer level flat no-lead semiconductor packages and methods of manu...

Semiconductor chip package with resilient conductive paste post and...

Leadframe having organic, polymerizable photo-imageable adhesion layer

Integrated circuit structures in package substrates

Protection from ESD during the manufacturing process of semiconduct...

Lead frame and method for manufacturing the same

Integrated circuit package having a raised lead edge

Semiconductor device and method of forming PIP with inner known goo...

Carrier-free semiconductor package and fabrication method

Patents Applicationslast 30 patents

Semiconductor Package and Method for Fabricating a Semiconductor Pa...

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

METHOD OF MANUFACTURING DIE PACKAGE STRUCTURE

LEAD FRAME, PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME

LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUF...

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

SUBSTRATES FOR SEMICONDUCTOR PACKAGES

METHOD FOR CONTACTING A BURIED INTERCONNECT RAIL OF AN INTEGRATED C...

METHOD FOR FABRICATING CARRIER-FREE SEMICONDUCTOR PACKAGE

PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME

PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCT...

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...

WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...

WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...

Integrated Circuit Package Having A Raised Lead Edge

THERMOSONICALLY BONDED CONNECTION FOR FLIP CHIP PACKAGES

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUF...

PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...

LEAD FRAME

PROCESS FOR FORMING LEADFRAME HAVING ORGANIC, POLYMERIZABLE PHOTO-I...

Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer

METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE

LEAD CARRIER WITH PRINT FORMED PACKAGE COMPONENTS AND CONDUCTIVE PA...

CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD