Folded bit line dram configuration

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CPC
Y10S257/907

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S257/00Active solid-state devices

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Y10S257/907Folded bit line dram configuration

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Patents Grantslast 30 patents

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Bit line barrier metal layer for semiconductor device and process f...
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Semiconductor substrate having first and second pairs of word lines
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Selective polysilicon stud growth
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Patents Applicationslast 30 patents

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Bit line barrier metal layer for semiconductor device and process f...
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Semiconductor memory devices having conductive line in twisted area...
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Selective polysilicon stud growth
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Folded bit line dram configuration

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of forming semiconductor device including protrusion type is...

Semiconductor device including protrusion type isolation layer

Semiconductor integrated circuit devices having contacts formed of...

Semiconductor device

High density memory array having increased channel widths

Error detection/correction method

Semiconductor device

Semiconductor device capable of preventing moisture-absorption of f...

Memory device with active layer of dendrimeric material

Bit line barrier metal layer for semiconductor device and process f...

Semiconductor device having both memory and logic circuit and its m...

Single-mask phase change memory element

Methods of forming memory circuitry

High density memory devices having improved channel widths and cell...

Selective polysilicon stud growth

Semiconductor device

Memory cell arrays

Bit line barrier metal layer for semiconductor device and process f...

Semiconductor substrate having first and second pairs of word lines

High density access transistor having increased channel width and m...

Semiconductor device and method of manufacturing the same

Semiconductor memory devices having conductive line in twisted area...

Semiconductor device

High density memory array having increased channel widths

Integrated circuit device having non-linear active area pillars

Method for forming storage node contact plug of DRAM (dynamic rando...

Methods of forming memory circuitry

Memory cell arrays

Semiconductor device having both memory and logic circuit and its m...

Selective polysilicon stud growth

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE INCLUDING PROTRUSION TYPE ISOLATION LAYER

Semiconductor device including protrusion type isolation layer

Semiconductor integrated circuit devices and fabrication methods th...

Error Detection/Correction Method

Semiconductor device

Memory device with improved data retention

Semiconductor device

Semiconductor device

Semiconductor device

Bit Line Barrier Metal Layer for Semiconductor Device and Process f...

Single-Mask Phase Change Memory Element

High density memory array having increased channel widths

DRAM memory device

Bit line barrier metal layer for semiconductor device and process f...

High density memory devices having improved channel widths and cell...

Integrated circuit device having non-linear active area pillars

Methods of forming memory circuitry

High density memory array having increased channel widths

Memory cell arrays

High density access transistor having increased channel width and m...

Semiconductor device

Semiconductor device having both memory and logic circuit and its m...

Semiconductor device capable of preventing moisture-absorption of f...

Semiconductor device

Semiconductor device and method of manufacturing the same

Methods of forming memory circuitry

Semiconductor memory devices having conductive line in twisted area...

Selective polysilicon stud growth

METHODS OF FORMING MEMORY CIRCUITRY

Latched sense amplifiers as high speed memory in a memory system