Integrated circuit memory devices having multi-bit normal memory cells and single-bit redundant memory cells therein

Abstract

A memory device includes a first memory array having a plurality of rows and columns of multi-bit DRAM cells therein. A redundant memory array is also provided having a plurality of single-bit memory cells therein. These single-bit memory cells are configured to support replacement of a first plurality of multi-bit memory cells within the first memory array, in response to detecting at least one defective multi-bit memory cell within the first plurality of multi-bit memory cells. This first plurality of multi-bit memory cells may be a column or row of multi-bit memory cells containing at least one defective multi-bit memory cell therein.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram of a conventional multi-level dynamic random access memory (DRAM), which includes a plurality of multi-level cells (MLCs) each storing 2-bit data;

FIG. 2 is a circuit diagram of a conventional multi-level DRAM, which includes a MLC array and a redundant MLC array;

FIG. 3 is a circuit diagram illustrating a multi-level DRAM according to an embodiment of the present invention; and

FIG. 4 is a schematic diagram illustrating an X8 data input/output circuit of the multi-level DRAM illustrated in FIG. 3.

Claims

1. An integrated circuit memory device, comprising: a first memory array having a plurality of rows and columns of multi-bit memory cells therein; anda redundant memory array having a plurality of single-bit memory cells therein that are configured to support replacement of a first plurality of multi-bit memory cells within said first memory array, in response to detecting at least one defective multi-bit memory cell within the first plurality of multi-bit memory cells.

2. The memory device of claim 1, wherein the multi-bit memory cells are 2-bit memory cells; and wherein the plurality of single-bit memory cells are arranged as a least significant bit (LSB) column of single-bit memory cells and a most significant bit (MSB) column of single-bit memory cells.

3. The memory device of claim 2, wherein a first column of multi-bit memory cells in said first memory array includes a first pair of differential bit lines, which are each divided into corresponding first and second bit line segments, and a first pair of transmission gates that electrically couple corresponding ones of the first and second bit line segments together in response to an asserted transmission gate signal.

4. The memory device of claim 3, wherein a pair of differential bit lines associated with the LSB column of single-bit memory cells are continuous bit lines that are uninterrupted by transmission gates.

5. The memory device of claim 2, wherein a layout area associated with the LSB and MSB columns of single-bit memory cells is about two times a layout area associated with a column of multi-bit memory cells in said first memory array.

6. An integrated circuit memory device, comprising: a first memory array having a plurality of rows and columns of multi-bit DRAM cells therein; anda redundant memory array having a plurality of single-bit DRAM cells therein that are configured to support replacement of a first plurality of multi-bit DRAM cells within said first memory array, in response to detecting at least one defective multi-bit DRAM cell within the first plurality of multi-bit DRAM cells.

7. The memory device of claim 6, wherein the multi-bit DRAM cells are 2-bit DRAM cells; and wherein the plurality of single-bit DRAM cells are arranged as a least significant bit (LSB) column of single-bit DRAM cells and a most significant bit (MSB) column of single-bit DRAM cells.

8. The memory device of claim 6, wherein a layout area associated with the LSB and MSB columns of single-bit DRAM cells is about two times a layout area associated with a column of multi-bit DRAM cells in said first memory array.

9. A method of operating an integrated circuit memory device, comprising the steps of: testing a first memory array having a plurality of rows and columns of multi-bit memory cells therein to detect a presence of at least one defective multi-bit memory cell in the first memory array; andreplacing a plurality of multi-bit memory cells including the defective multi-bit memory cell with a plurality of single-bit memory cells.

10. The method of claim 9, wherein said replacing step comprises replacing a column of multi-bit memory cells including the defective multi-bit memory cell with at least two columns of single-bit memory cells;

11-34. (canceled)