forming at least one of the output signals directly from the minterms of the input signals

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/5016forming at least one of the output signals directly from the minterms of the input signals

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Patents Grantslast 30 patents

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Performance power optimized full adder
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- Issue date Apr 7, 2020
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Checksum adder
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Checksum adder
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- Issue date Sep 19, 2017
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- International Business Machines Corporation
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Checksum adder
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Arithmetic circuit and method of driving the same
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Methods and apparatus for sum of address compare write recode and c...
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Standard cell for arithmetic logic unit and chip card controller
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Logic gate with a reduced number of switches, especially for applic...
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Standard cell for arithmetic logic unit and chip card controller
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Arithmetic unit of arbitrary precision, operation method for proces...
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Symmetric cascaded domino carry generate circuit
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Digital multiplier with reduced spurious switching by means of Latc...
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Simultaneous dual rail static carry-save-adder circuit using silico...
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4 to 2 adder
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Logical circuit
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Method and apparatus for enhancing noise tolerance in dynamic silic...
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Reversible adiabatic logic circuit and pipelined reversible adiabat...
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Method and apparatus for saturation in an N-NARY adder/subtractor
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Energy economized pass-transistor logic circuit and full adder usin...
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Full adder circuit
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- Issue date Feb 23, 1999
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Patents Applicationslast 30 patents

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FEEDBACK APPARATUS AND FFT/IFFT PROCESSOR
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- Jianbiao HE
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PERFORMANCE POWER OPTIMIZED FULL ADDER
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DIGITAL BIT-SERIAL MULTI-MULTIPLY-AND-ACCUMULATE COMPUTE IN MEMORY
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CHECKSUM ADDER
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ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME
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- International Buisness Machines Corp.
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Logical circuit
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- G06 - COMPUTING CALCULATING COUNTING

forming at least one of the output signals directly from the minterms of the input signals

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Digital bit-serial multi-multiply-and-accumulate compute in memory

Performance power optimized full adder

Arithmetic circuit and method of driving the same

Checksum adder

Checksum adder

Checksum adder

Checksum adder

Arithmetic circuit and method of driving the same

Methods and apparatus for sum of address compare write recode and c...

Standard cell for arithmetic logic unit and chip card controller

Logic gate with a reduced number of switches, especially for applic...

Standard cell for arithmetic logic unit and chip card controller

Arithmetic unit of arbitrary precision, operation method for proces...

Adder-rounder circuitry for specialized processing block in program...

Symmetric cascaded domino carry generate circuit

Digital multiplier with reduced spurious switching by means of Latc...

Simultaneous dual rail static carry-save-adder circuit using silico...

4 to 2 adder

Logical circuit

Method and apparatus for enhancing noise tolerance in dynamic silic...

Reversible adiabatic logic circuit and pipelined reversible adiabat...

Method and apparatus for dynamic partitionable saturating adder/sub...

Method and apparatus for saturation in an N-NARY adder/subtractor

Energy economized pass-transistor logic circuit and full adder usin...

Operation circuit

Logic blocks with mixed low and regular V.sub.t MOSFET devices for...

Digital adder

Full adder using NMOS transistor

Full adder circuit

Full subtracter

Patents Applicationslast 30 patents

FEEDBACK APPARATUS AND FFT/IFFT PROCESSOR

PERFORMANCE POWER OPTIMIZED FULL ADDER

DIGITAL BIT-SERIAL MULTI-MULTIPLY-AND-ACCUMULATE COMPUTE IN MEMORY

CHECKSUM ADDER

CHECKSUM ADDER

ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME

ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME

Methods and Apparatus for Sum of Address Compare Write Recode and C...

STANDARD CELL FOR ARITHMETIC LOGIC UNIT AND CHIP CARD CONTROLLER

LOGIC GATE WITH A REDUCED NUMBER OF SWITCHES, ESPECIALLY FOR APPLIC...

Standard cell for arithmetic logic unit and chip card controller

Standard cell for arithmetic logic unit and chip card controller

3:2 Bit compressor circuit and method

Arithmetic unit of arbitrary precision, operation method for proces...

Digital Multiplier with reduced spurious switching by means of Latc...

Symmetric cascaded domino carry generate circuit

Simultaneous dual rail static carry-save-adder circuit

Logical circuit