Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

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G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Industries

Patents Grantslast 30 patents

Information Patent Grant
Address scheduling methods for non-volatile memory devices with thr...
- Patent number 12,147,340
- Issue date Nov 19, 2024
- Samsung Electronics Co., Ltd.
- Chi Weon Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices including stack structure having gate region...
- Patent number 12,137,555
- Issue date Nov 5, 2024
- Samsung Electronics Co., Ltd.
- Geunwon Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic devices comprising capacitor structures, and relate...
- Patent number 12,137,549
- Issue date Nov 5, 2024
- Micron Technology, Inc.
- Fatma Arzum Simsek-Ege
- G11 - INFORMATION STORAGE
Information Patent Grant
Structures for word line multiplexing in three-dimensional memory a...
- Patent number 12,131,794
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Fatma Arzum Simsek-Ege
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory bandwidth aggregation using simultaneous access of stacked s...
- Patent number 12,131,796
- Issue date Oct 29, 2024
- RAMBUS INC.
- Yohan Frans
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and semiconductor device including the same
- Patent number 12,125,515
- Issue date Oct 22, 2024
- Samsung Electronics Co., Ltd.
- Sang-Hoon Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device architecture
- Patent number 12,119,055
- Issue date Oct 15, 2024
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for reducing voltage degradation caused by parasitic resist...
- Patent number 12,106,801
- Issue date Oct 1, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jhon Jhy Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and layout, manufacturing method of the same
- Patent number 12,101,922
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Te-Hsin Chiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device layout with intersecting region between sub-wordline...
- Patent number 12,094,520
- Issue date Sep 17, 2024
- Micron Technology, Inc.
- Harish Gadamsetty
- G11 - INFORMATION STORAGE
Information Patent Grant
3D NAND flash memory devices, and related electronic systems
- Patent number 12,096,626
- Issue date Sep 17, 2024
- Kunal R. Parekh
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and cache circuit configuration
- Patent number 12,093,176
- Issue date Sep 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsien-Hsin Sean Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and data storage system including the same
- Patent number 12,096,625
- Issue date Sep 17, 2024
- Samsung Electronics Co., Ltd.
- Yoonjo Hwang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of performing internal processing operations with pre-define...
- Patent number 12,087,388
- Issue date Sep 10, 2024
- Samsung Electronics Co., Ltd.
- Hak-Soo Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-deck non-volatile memory architecture with improved wordline...
- Patent number 12,087,350
- Issue date Sep 10, 2024
- Intel Corporation
- William Waller
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor structure and formation method thereof
- Patent number 12,082,401
- Issue date Sep 3, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Xinman Cao
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit module with improved line load
- Patent number 12,080,368
- Issue date Sep 3, 2024
- M31 Technology Corporation
- Nan-Chun Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device with variable resistance layers and insulating la...
- Patent number 12,075,632
- Issue date Aug 27, 2024
- SK Hynix Inc.
- Si Jung Yoo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and data processing system including the same
- Patent number 12,073,217
- Issue date Aug 27, 2024
- SK Hynix Inc.
- Dong Uk Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture of three-dimensional memory device and methods regardi...
- Patent number 12,068,192
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Microelectronic devices including stack structures having air gaps,...
- Patent number 12,052,862
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Byeung Chul Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory stacks connected to processing units and assoc...
- Patent number 12,046,559
- Issue date Jul 23, 2024
- Micron Technology, Inc.
- Kyle K. Kirby
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming a structure with a hole
- Patent number 12,040,229
- Issue date Jul 16, 2024
- ASM IP Holding B.V.
- Dieter Pierreux
- G11 - INFORMATION STORAGE
Information Patent Grant
Perimeter trench formation and delineation etch delayering
- Patent number 12,040,196
- Issue date Jul 16, 2024
- FEI Company
- James Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
Control logic assemblies
- Patent number 12,040,041
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of forming microelectronic devices
- Patent number 12,041,769
- Issue date Jul 16, 2024
- John D. Hopkins
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and data processing system including the same
- Patent number 12,039,333
- Issue date Jul 16, 2024
- SK Hynix Inc.
- Dong Uk Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package-on-package (PoP) semiconductor package and electronic syste...
- Patent number 12,033,991
- Issue date Jul 9, 2024
- Samsung Electronics Co., Ltd.
- Tong-suk Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Interconnect architecture for three-dimensional processing systems
- Patent number 12,033,714
- Issue date Jul 9, 2024
- Advanced Micro Devices, Inc.
- Nuwan S. Jayasena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor structures and methods for forming the same
- Patent number 12,027,422
- Issue date Jul 2, 2024
- Winbond Electronics Corp.
- Tseng-Yao Pan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS OF MANUFACTURING MEMORY ARRAY AND INTEGRATED CIRCUIT
- Publication number 20240387475
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Sheng Yun
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY STACKS CONNECTED TO PROCESSING UNITS AND ASSOC...
- Publication number 20240379568
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Kyle K. Kirby
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20240373616
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Te-Hsin Chiu
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC DEVICES AND MEMORY DEVICES
- Publication number 20240349498
- Publication date Oct 17, 2024
- Lodestar Licensing Group LLC
- John D. Hopkins
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME
- Publication number 20240338215
- Publication date Oct 10, 2024
- SK HYNIX INC.
- Dong Uk LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES
- Publication number 20240324223
- Publication date Sep 26, 2024
- Lodestar Licensing Group LLC
- S. M. Istiaque Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTE...
- Publication number 20240321842
- Publication date Sep 26, 2024
- Samsung Electronics Co., Ltd.
- Tong-Suk Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CHIP
- Publication number 20240312555
- Publication date Sep 19, 2024
- WINBOND ELECTRONICS CORP.
- Ying-Te Tu
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE LOCATION LOAD CONTROL SYSTEM
- Publication number 20240292502
- Publication date Aug 29, 2024
- Lutron Technology Company LLC
- Russell Weightman
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20240268109
- Publication date Aug 8, 2024
- KIOXIA Corporation
- Yusuke Shima
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DA...
- Publication number 20240257863
- Publication date Aug 1, 2024
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED DRAM DEVICE AND METHOD OF MANUFACTURE
- Publication number 20240242741
- Publication date Jul 18, 2024
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM CELL AND MRAM
- Publication number 20240224813
- Publication date Jul 4, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Perng-Fei YUH
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME
- Publication number 20240221799
- Publication date Jul 4, 2024
- KIOXIA Corporation
- Akio SUGAHARA
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF FORMING MICROELECTRONIC DEVICES
- Publication number 20240215232
- Publication date Jun 27, 2024
- Micron Technology, Inc.
- Shuangqiang Luo
- G11 - INFORMATION STORAGE
Information Patent Application
U-TURN CIRCUITRY TO CONVERT INTER-LAYER CONNECTIONS OF AN INTEGRATE...
- Publication number 20240194645
- Publication date Jun 13, 2024
- Xilinx, Inc.
- Jay T. YOUNG
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED M...
- Publication number 20240196606
- Publication date Jun 13, 2024
- Micron Technology, Inc.
- Lifang Xu
- G11 - INFORMATION STORAGE
Information Patent Application
Sub-Word Line Driver Placement For Memory Device
- Publication number 20240185911
- Publication date Jun 6, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING SUPPORT PILLARS
- Publication number 20240188288
- Publication date Jun 6, 2024
- Lodestar Licensing Group LLC
- Shuangqiang Luo
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRAT...
- Publication number 20240177743
- Publication date May 30, 2024
- Micron Technology, Inc.
- James S. Rehmeyer
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL MEMORY CELLS
- Publication number 20240172442
- Publication date May 23, 2024
- KIOXIA Corporation
- Fumihiro KONO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Assemblies Having Transistor Body Regions Coupled to Car...
- Publication number 20240172432
- Publication date May 23, 2024
- Micron Technology, Inc.
- Kamal M. Karda
- G11 - INFORMATION STORAGE
Information Patent Application
Memory System Having Combined High Density, Low Bandwidth and Low D...
- Publication number 20240161804
- Publication date May 16, 2024
- Apple Inc.
- Sukalpa Biswas
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20240155838
- Publication date May 9, 2024
- SK HYNIX INC.
- Nam Jae LEE
- G11 - INFORMATION STORAGE
Information Patent Application
CONDUCTIVE LINE CONTACT REGIONS HAVING MULTIPLE MULTI-DIRECTION CON...
- Publication number 20240147693
- Publication date May 2, 2024
- Micron Technology, Inc.
- Byung Yoon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Write Driver Boost Circuit for Memory Cells
- Publication number 20240135983
- Publication date Apr 25, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Application
UNIFIED MICRO SYSTEM WITH MEMORY INTEGRATED CIRCUIT AND LOGIC INTEG...
- Publication number 20240114678
- Publication date Apr 4, 2024
- ETRON TECHNOLOGY, INC.
- Chao-Chun Lu
- G11 - INFORMATION STORAGE
Information Patent Application
ARRANGEMENTS FOR MEMORY WITH ONE ACCESS TRANSISTOR FOR MULTIPLE CAP...
- Publication number 20240107749
- Publication date Mar 28, 2024
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY ROUTING TECHNIQUES
- Publication number 20240096852
- Publication date Mar 21, 2024
- Lodestar Licensing Group, LLC
- Brent Keeth
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
- Publication number 20240088900
- Publication date Mar 14, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE

Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Address scheduling methods for non-volatile memory devices with thr...

Semiconductor devices including stack structure having gate region...

Microelectronic devices comprising capacitor structures, and relate...

Structures for word line multiplexing in three-dimensional memory a...

Memory bandwidth aggregation using simultaneous access of stacked s...

Memory device and semiconductor device including the same

Memory device architecture

Circuit for reducing voltage degradation caused by parasitic resist...

Memory device and layout, manufacturing method of the same

Memory device layout with intersecting region between sub-wordline...

3D NAND flash memory devices, and related electronic systems

Memory circuit and cache circuit configuration

Semiconductor device and data storage system including the same

Method of performing internal processing operations with pre-define...

Multi-deck non-volatile memory architecture with improved wordline...

Semiconductor structure and formation method thereof

Circuit module with improved line load

Electronic device with variable resistance layers and insulating la...

Memory system and data processing system including the same

Architecture of three-dimensional memory device and methods regardi...

Microelectronic devices including stack structures having air gaps,...

Semiconductor memory stacks connected to processing units and assoc...

Method for forming a structure with a hole

Perimeter trench formation and delineation etch delayering

Control logic assemblies

Methods of forming microelectronic devices

Memory system and data processing system including the same

Package-on-package (PoP) semiconductor package and electronic syste...

Interconnect architecture for three-dimensional processing systems

Semiconductor structures and methods for forming the same

Patents Applicationslast 30 patents

METHODS OF MANUFACTURING MEMORY ARRAY AND INTEGRATED CIRCUIT

SEMICONDUCTOR MEMORY STACKS CONNECTED TO PROCESSING UNITS AND ASSOC...

TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

MICROELECTRONIC DEVICES AND MEMORY DEVICES

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME

INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES

PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTE...

MEMORY CHIP

MULTIPLE LOCATION LOAD CONTROL SYSTEM

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DA...

STACKED DRAM DEVICE AND METHOD OF MANUFACTURE

MRAM CELL AND MRAM

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME

METHODS OF FORMING MICROELECTRONIC DEVICES

U-TURN CIRCUITRY TO CONVERT INTER-LAYER CONNECTIONS OF AN INTEGRATE...

MICROELECTRONIC DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED M...

Sub-Word Line Driver Placement For Memory Device

MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING SUPPORT PILLARS

METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRAT...

SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL MEMORY CELLS

Integrated Assemblies Having Transistor Body Regions Coupled to Car...

Memory System Having Combined High Density, Low Bandwidth and Low D...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

CONDUCTIVE LINE CONTACT REGIONS HAVING MULTIPLE MULTI-DIRECTION CON...

Write Driver Boost Circuit for Memory Cells

UNIFIED MICRO SYSTEM WITH MEMORY INTEGRATED CIRCUIT AND LOGIC INTEG...

ARRANGEMENTS FOR MEMORY WITH ONE ACCESS TRANSISTOR FOR MULTIPLE CAP...

STACKED MEMORY ROUTING TECHNIQUES

MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY