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G01R31/318561

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318561Identification of the subpart

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Patents Grantslast 30 patents

Information Patent Grant
Circuit and method for diagnosing scan chain failures
- Patent number 10,371,751
- Issue date Aug 6, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated defect detection and location systems and methods in sem...
- Patent number 10,168,387
- Issue date Jan 1, 2019
- Infineon Technologies Austria AG
- Cheow Guan Lim
- G01 - MEASURING TESTING
Information Patent Grant
Testing multi-core integrated circuit with parallel scan test data...
- Patent number 10,054,637
- Issue date Aug 21, 2018
- NXP USA, INC.
- Zhiyong Hao
- G01 - MEASURING TESTING
Information Patent Grant
Test apparatus for generating reference scan chain test data and te...
- Patent number 9,885,752
- Issue date Feb 6, 2018
- Advantest Corporation
- Markus Seuring
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for diagnosing scan chain failures
- Patent number 9,791,510
- Issue date Oct 17, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Error detection in stored data values
- Patent number 9,760,438
- Issue date Sep 12, 2017
- ARM Limited
- Vikas Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for diagnosing scan chain failures
- Patent number 9,194,913
- Issue date Nov 24, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Tap linking module test access port controller with enable input
- Patent number 9,121,904
- Issue date Sep 1, 2015
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Functional fabric based test wrapper for circuit testing of IP blocks
- Patent number 9,043,665
- Issue date May 26, 2015
- Intel Corporation
- Srinivas Patil
- G01 - MEASURING TESTING
Information Patent Grant
Tap controller having TMS, TCK, enable inputs and control outputs
- Patent number 8,935,585
- Issue date Jan 13, 2015
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Selecting an IC core tap linking module for scanning data
- Patent number 8,751,883
- Issue date Jun 10, 2014
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device having input/output wrappers, and a method of...
- Patent number 8,732,540
- Issue date May 20, 2014
- Samsung Electronics Co., Ltd.
- JongPil Lee
- G01 - MEASURING TESTING
Information Patent Grant
Heterogeneous multi-core integrated circuit and method for debuggin...
- Patent number 8,666,690
- Issue date Mar 4, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Amar Nath Deogharia
- G01 - MEASURING TESTING
Information Patent Grant
Verifying and detecting boundary scan cells to input/output mapping
- Patent number 8,656,235
- Issue date Feb 18, 2014
- International Business Machines Corporation
- Benedikt Geukes
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for diagnosing scan chain failures
- Patent number 8,566,657
- Issue date Oct 22, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
TAPS and hierarchical TLM with shift register and state machines
- Patent number 8,516,319
- Issue date Aug 20, 2013
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Taps and hierarchical TLM with shift register, and state machine
- Patent number 8,356,219
- Issue date Jan 15, 2013
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
HTMLS with first and second select outputs and enable inputs
- Patent number 8,234,529
- Issue date Jul 31, 2012
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test device and method for hierarchical test architecture
- Patent number 8,185,782
- Issue date May 22, 2012
- Industrial Technology Research Institute
- Kun-Lun Luo
- G01 - MEASURING TESTING
Information Patent Grant
Tap demultiplexer with select and select one outputs for HTML
- Patent number 7,962,815
- Issue date Jun 14, 2011
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Separate scan cell in series with TAP instruction register
- Patent number 7,774,664
- Issue date Aug 10, 2010
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Multicore chip test
- Patent number 7,689,884
- Issue date Mar 30, 2010
- Advanced Micro Devices, Inc.
- Markus Seuring
- G01 - MEASURING TESTING
Information Patent Grant
Tap with separate scan cell in series with instruction register
- Patent number 7,185,250
- Issue date Feb 27, 2007
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Substrate configurable JTAG ID scheme
- Patent number 7,131,033
- Issue date Oct 31, 2006
- Cypress Semiconductor Corp.
- Weston Roper
- G11 - INFORMATION STORAGE
Information Patent Grant
Test arrangement for assemblages of intergrated circuit blocks
- Patent number 6,988,230
- Issue date Jan 17, 2006
- Koninklijke Philips Electronics N.V.
- Hubertus Gerardus Hendrikus Vermeulen
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical linking module connection to access ports of embedded...
- Patent number 6,975,980
- Issue date Dec 13, 2005
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Technique for debugging an integrated circuit having a parallel sca...
- Patent number 6,941,498
- Issue date Sep 6, 2005
- Agilent Technologies, Inc.
- Ismed D. S. Hartano
- G01 - MEASURING TESTING
Information Patent Grant
Soft coding of multiple device IDs for IEEE compliant JTAG devices
- Patent number 6,848,068
- Issue date Jan 25, 2005
- Cypress Semiconductor Corp.
- Zhiwu Liu
- G01 - MEASURING TESTING
Information Patent Grant
Method for digital compression of characters
- Patent number 6,603,414
- Issue date Aug 5, 2003
- Compaq Computer Corporation
- L. John Postas
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical access of test access ports in embedded core integrate...
- Patent number 6,408,413
- Issue date Jun 18, 2002
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
FLEXIBLE INTERFACE
- Publication number 20210374023
- Publication date Dec 2, 2021
- STMicroelectronics (Research and Development) Limited
- Leonardo NAPOLITANO
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES
- Publication number 20180031634
- Publication date Feb 1, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20140229781
- Publication date Aug 14, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES
- Publication number 20140068362
- Publication date Mar 6, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20130305109
- Publication date Nov 14, 2013
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
VERIFYING AND DETECTING BOUNDARY SCAN CELLS TO INPUT/OUTPUT MAPPING
- Publication number 20130139014
- Publication date May 30, 2013
- International Business Machines Corporation
- Benedikt Geukes
- G01 - MEASURING TESTING
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20130103996
- Publication date Apr 25, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
HETEROGENEOUS MULTI-CORE INTEGRATED CIRCUIT AND METHOD FOR DEBUGGIN...
- Publication number 20130090887
- Publication date Apr 11, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Amar Nath Deogharia
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES
- Publication number 20120278671
- Publication date Nov 1, 2012
- Taiwan Semiconductor Manufacturing Co., LTD
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
FUNCTIONAL FABRIC BASED TEST WRAPPER FOR CIRCUIT TESTING OF IP BLOCKS
- Publication number 20120233514
- Publication date Sep 13, 2012
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20120221907
- Publication date Aug 30, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE HAVING INPUT/OUTPUT WRAPPERS, AND A METHOD OF...
- Publication number 20110279160
- Publication date Nov 17, 2011
- JongPil Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20110214028
- Publication date Sep 1, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20100275078
- Publication date Oct 28, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST DEVICE AND METHOD FOR HIERARCHICAL TEST ARCHITECTURE
- Publication number 20090259889
- Publication date Oct 15, 2009
- Industrial Technology Research Institute
- Kun-Lun Luo
- G01 - MEASURING TESTING
Information Patent Application
Multicore chip test
- Publication number 20080148117
- Publication date Jun 19, 2008
- Advanced Micro Devices, Inc.
- Markus Seuring
- G01 - MEASURING TESTING
Information Patent Application
JTAG boundary scan compliant testing architecture with full and par...
- Publication number 20080082879
- Publication date Apr 3, 2008
- Amar Guettaf
- G01 - MEASURING TESTING
Information Patent Application
HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...
- Publication number 20070118780
- Publication date May 24, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical access of test access ports in embedded core integrate...
- Publication number 20050050414
- Publication date Mar 3, 2005
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical test methodology for multi-core chips
- Publication number 20040006729
- Publication date Jan 8, 2004
- Rajesh Y. Pendurkar
- G01 - MEASURING TESTING
Information Patent Application
Technique for debugging an integrated circuit having a parallel sca...
- Publication number 20030172334
- Publication date Sep 11, 2003
- Ismed D.S. Hartano
- G01 - MEASURING TESTING
Information Patent Application
Electronic device
- Publication number 20030079166
- Publication date Apr 24, 2003
- Hubertus Gerardus Hendrikus Vermeulen
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical access of test access ports in embedded core integrate...
- Publication number 20020162063
- Publication date Oct 31, 2002
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for integrated circuit debugging
- Publication number 20020133794
- Publication date Sep 19, 2002
- Ruban Kanapathippillai
- G01 - MEASURING TESTING

Identification of the subpart

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Circuit and method for diagnosing scan chain failures

Integrated defect detection and location systems and methods in sem...

Testing multi-core integrated circuit with parallel scan test data...

Test apparatus for generating reference scan chain test data and te...

Circuit and method for diagnosing scan chain failures

Error detection in stored data values

Circuit and method for diagnosing scan chain failures

Tap linking module test access port controller with enable input

Functional fabric based test wrapper for circuit testing of IP blocks

Tap controller having TMS, TCK, enable inputs and control outputs

Selecting an IC core tap linking module for scanning data

Semiconductor device having input/output wrappers, and a method of...

Heterogeneous multi-core integrated circuit and method for debuggin...

Verifying and detecting boundary scan cells to input/output mapping

Circuit and method for diagnosing scan chain failures

TAPS and hierarchical TLM with shift register and state machines

Taps and hierarchical TLM with shift register, and state machine

HTMLS with first and second select outputs and enable inputs

Test device and method for hierarchical test architecture

Tap demultiplexer with select and select one outputs for HTML

Separate scan cell in series with TAP instruction register

Multicore chip test

Tap with separate scan cell in series with instruction register

Substrate configurable JTAG ID scheme

Test arrangement for assemblages of intergrated circuit blocks

Hierarchical linking module connection to access ports of embedded...

Technique for debugging an integrated circuit having a parallel sca...

Soft coding of multiple device IDs for IEEE compliant JTAG devices

Method for digital compression of characters

Hierarchical access of test access ports in embedded core integrate...

Patents Applicationslast 30 patents

FLEXIBLE INTERFACE

CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

VERIFYING AND DETECTING BOUNDARY SCAN CELLS TO INPUT/OUTPUT MAPPING

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

HETEROGENEOUS MULTI-CORE INTEGRATED CIRCUIT AND METHOD FOR DEBUGGIN...

CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES

FUNCTIONAL FABRIC BASED TEST WRAPPER FOR CIRCUIT TESTING OF IP BLOCKS

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

SEMICONDUCTOR DEVICE HAVING INPUT/OUTPUT WRAPPERS, AND A METHOD OF...

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

TEST DEVICE AND METHOD FOR HIERARCHICAL TEST ARCHITECTURE

Multicore chip test

JTAG boundary scan compliant testing architecture with full and par...

HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATE...

Hierarchical access of test access ports in embedded core integrate...

Hierarchical test methodology for multi-core chips

Technique for debugging an integrated circuit having a parallel sca...

Electronic device

Hierarchical access of test access ports in embedded core integrate...

Method and apparatus for integrated circuit debugging