in serial memories

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CPC
G11C29/003

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/003in serial memories

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Test interface board having a transmission line to merge signals, t...
- Patent number 10,782,349
- Issue date Sep 22, 2020
- Samsung Electronics Co., Ltd.
- Yongjeong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing optimizations in circuit designs using opposite clock edge t...
- Patent number 10,416,232
- Issue date Sep 17, 2019
- Xilinx, Inc.
- Guenter Stenz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for master-slave detection
- Patent number 9,881,658
- Issue date Jan 30, 2018
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Information processing system, information compression device, info...
- Patent number 9,553,604
- Issue date Jan 24, 2017
- NEC Corporation
- Hiroaki Inoue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Embedded resilient buffer
- Patent number 9,337,952
- Issue date May 10, 2016
- Intel Corporation
- Somnath Paul
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer memory test structure
- Patent number 8,924,805
- Issue date Dec 30, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for master-slave detection
- Patent number 8,862,863
- Issue date Oct 14, 2014
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer memory test structure
- Patent number 8,667,354
- Issue date Mar 4, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for master-slave detection
- Patent number 8,499,187
- Issue date Jul 30, 2013
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer memory test structure
- Patent number 8,386,867
- Issue date Feb 26, 2013
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM macro test flop
- Patent number 8,181,073
- Issue date May 15, 2012
- Oracle America, Inc.
- Ali Vahidsafa
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for testing multi-device systems
- Patent number 8,081,529
- Issue date Dec 20, 2011
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and mechanism for implementation-independent, on-line, end-t...
- Patent number 8,024,632
- Issue date Sep 20, 2011
- Victor Konrad
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting a digital delay function of a data memory unit
- Patent number 7,933,156
- Issue date Apr 26, 2011
- Telefonaktiebolaget LM Ericsson (publ)
- Klaus W. Ruthemann
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for integrated circuit for measuring set-up and hold time...
- Patent number 7,930,663
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 7,925,944
- Issue date Apr 12, 2011
- Panasonic Corporation
- Masaya Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Diagnostic method and apparatus for non-destructively observing lat...
- Patent number 7,916,826
- Issue date Mar 29, 2011
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for testing multi-device systems
- Patent number 7,911,860
- Issue date Mar 22, 2011
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for testing multi-device systems
- Patent number 7,679,976
- Issue date Mar 16, 2010
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing a sequential access memory plane and a correspond...
- Patent number 7,661,040
- Issue date Feb 9, 2010
- STMicroelectronics S.A.
- Marc Beaujoin
- G11 - INFORMATION STORAGE
Information Patent Grant
Enabling special modes within a digital device
- Patent number 7,603,601
- Issue date Oct 13, 2009
- Microchip Technology Incorporated
- Cristian P. Masgras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable memory architecture with built-in testing mechanism
- Patent number 7,603,603
- Issue date Oct 13, 2009
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for testing a nonvolatile memory and a method thereof
- Patent number 7,554,879
- Issue date Jun 30, 2009
- Samsung Electronics Co., Ltd.
- Jong-Keun Ahn
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method to manage external voltage for semiconductor m...
- Patent number 7,525,856
- Issue date Apr 28, 2009
- Atmel Corporation
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for testing multi-device systems
- Patent number 7,508,724
- Issue date Mar 24, 2009
- Mosaid Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Diagnostic method and apparatus for non-destructively observing lat...
- Patent number 7,453,973
- Issue date Nov 18, 2008
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge-triggered master + LSSD slave binary latch
- Patent number 7,401,278
- Issue date Jul 15, 2008
- International Business Machines Corporation
- Peter Verwegen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test engine
- Patent number 7,395,169
- Issue date Jul 1, 2008
- Dialog Semiconductor
- Hans Martin Vonstaudt
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing propagation delay of a shift register using a ring oscillator
- Patent number 7,305,599
- Issue date Dec 4, 2007
- Xilinx, Inc.
- Richard D. J. Duce
- G11 - INFORMATION STORAGE
Information Patent Grant
Error bit method and circuitry for oscillation-based characterization
- Patent number 7,210,078
- Issue date Apr 24, 2007
- Texas Instruments Incorporated
- Brian D. Borchers
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TEST INTERFACE BOARD HAVING A TRANSMISSION LINE TO MERGE SIGNALS, T...
- Publication number 20190004113
- Publication date Jan 3, 2019
- Samsung Electronics Co., Ltd.
- YONGJEONG KIM
- G11 - INFORMATION STORAGE
Information Patent Application
EMBEDDED RESILIENT BUFFER
- Publication number 20140317458
- Publication date Oct 23, 2014
- Somnath Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER MEMORY TEST STRUCTURE
- Publication number 20140115414
- Publication date Apr 24, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION
- Publication number 20130311818
- Publication date Nov 21, 2013
- Micron Technology, Inc.
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER MEMORY TEST STRUCTURE
- Publication number 20130173974
- Publication date Jul 4, 2013
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION
- Publication number 20130042138
- Publication date Feb 14, 2013
- Micron Technology, Inc.
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
- Publication number 20110141835
- Publication date Jun 16, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Hong Beom PYEON
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM MACRO TEST FLOP
- Publication number 20110072326
- Publication date Mar 24, 2011
- SUN MICROSYSTEMS, INC.
- Ali Vahidsafa
- G01 - MEASURING TESTING
Information Patent Application
COMPUTER MEMORY TEST STRUCTURE
- Publication number 20110004793
- Publication date Jan 6, 2011
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
- Publication number 20100135092
- Publication date Jun 3, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Hong Beom PYEON
- G11 - INFORMATION STORAGE
Information Patent Application
Adjusting a Digital Delay Function of a Data Memory Unit
- Publication number 20090219771
- Publication date Sep 3, 2009
- Klaus W. Ruthemann
- G11 - INFORMATION STORAGE
Information Patent Application
DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...
- Publication number 20090180584
- Publication date Jul 16, 2009
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
- Publication number 20090161458
- Publication date Jun 25, 2009
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20090161813
- Publication date Jun 25, 2009
- Masaya Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR M...
- Publication number 20080246504
- Publication date Oct 9, 2008
- ATMEL CORPORATION
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIME...
- Publication number 20080201675
- Publication date Aug 21, 2008
- International Business Machines Corporation
- Larry Wissel
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
- Publication number 20080130386
- Publication date Jun 5, 2008
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH...
- Publication number 20080071489
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Larry Wissel
- G01 - MEASURING TESTING
Information Patent Application
Memory test engine
- Publication number 20070271059
- Publication date Nov 22, 2007
- Dialog Semiconductor GmbH
- Hans Martin Vonstaudt
- G01 - MEASURING TESTING
Information Patent Application
Apparatus for testing a nonvolatile memory and a method thereof
- Publication number 20070030755
- Publication date Feb 8, 2007
- SAMSUNG ELECTRONICS CO., LTD.
- Jong-Keun Ahn
- G11 - INFORMATION STORAGE
Information Patent Application
Diagnostic Method and Apparatus For Non-Destructively Observing Lat...
- Publication number 20070033458
- Publication date Feb 8, 2007
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable memory architecture with built-in testing mechanism
- Publication number 20070016826
- Publication date Jan 18, 2007
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
Enabling special modes within a digital device
- Publication number 20060190791
- Publication date Aug 24, 2006
- MICROCHIP TECHNOLOGY INCORPORATED
- Cristian P. Masgras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EDGE-TRIGGERED MASTER + LSSD SLAVE BINARY LATCH
- Publication number 20050216806
- Publication date Sep 29, 2005
- International Business Machines Corporation
- Peter Verwegen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus for testing a nonvolatile memory and a method thereof
- Publication number 20050146981
- Publication date Jul 7, 2005
- SAMSUNG ELECTRONICS CO., LTD.
- Jong-Keun Ahn
- G11 - INFORMATION STORAGE
Information Patent Application
Scan testable first-in first-out architecture
- Publication number 20050114612
- Publication date May 26, 2005
- Jerome Bombal
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for low overhead circuit scan
- Publication number 20050071717
- Publication date Mar 31, 2005
- International Business Machines Corp.
- Wendy Ann Belluomini
- G01 - MEASURING TESTING
Information Patent Application
DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...
- Publication number 20050025277
- Publication date Feb 3, 2005
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
Test structure and method for accurate determination of soft error...
- Publication number 20040187050
- Publication date Sep 23, 2004
- Robert Christopher Baumann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error bit method and circuitry for oscillation-based characterization
- Publication number 20040044934
- Publication date Mar 4, 2004
- Brian D. Borchers
- G11 - INFORMATION STORAGE

in serial memories

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test interface board having a transmission line to merge signals, t...

Timing optimizations in circuit designs using opposite clock edge t...

Methods and apparatuses for master-slave detection

Information processing system, information compression device, info...

Embedded resilient buffer

Computer memory test structure

Methods and apparatuses for master-slave detection

Computer memory test structure

Methods and apparatuses for master-slave detection

Computer memory test structure

SRAM macro test flop

Circuit and method for testing multi-device systems

Method and mechanism for implementation-independent, on-line, end-t...

Adjusting a digital delay function of a data memory unit

Structure for integrated circuit for measuring set-up and hold time...

Semiconductor device

Diagnostic method and apparatus for non-destructively observing lat...

Circuit and method for testing multi-device systems

Circuit and method for testing multi-device systems

Method of testing a sequential access memory plane and a correspond...

Enabling special modes within a digital device

Configurable memory architecture with built-in testing mechanism

Apparatus for testing a nonvolatile memory and a method thereof

Apparatus and method to manage external voltage for semiconductor m...

Circuit and method for testing multi-device systems

Diagnostic method and apparatus for non-destructively observing lat...

Edge-triggered master + LSSD slave binary latch

Memory test engine

Testing propagation delay of a shift register using a ring oscillator

Error bit method and circuitry for oscillation-based characterization

Patents Applicationslast 30 patents

TEST INTERFACE BOARD HAVING A TRANSMISSION LINE TO MERGE SIGNALS, T...

EMBEDDED RESILIENT BUFFER

COMPUTER MEMORY TEST STRUCTURE

METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION

COMPUTER MEMORY TEST STRUCTURE

METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION

CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS

SRAM MACRO TEST FLOP

COMPUTER MEMORY TEST STRUCTURE

CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS

Adjusting a Digital Delay Function of a Data Memory Unit

DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...

CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS

SEMICONDUCTOR DEVICE

APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR M...

STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIME...

CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS

INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH...

Memory test engine

Apparatus for testing a nonvolatile memory and a method thereof

Diagnostic Method and Apparatus For Non-Destructively Observing Lat...

Configurable memory architecture with built-in testing mechanism

Enabling special modes within a digital device

EDGE-TRIGGERED MASTER + LSSD SLAVE BINARY LATCH

Apparatus for testing a nonvolatile memory and a method thereof

Scan testable first-in first-out architecture

Method and apparatus for low overhead circuit scan

DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...

Test structure and method for accurate determination of soft error...

Error bit method and circuitry for oscillation-based characterization