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CPC
G01R31/31712

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/31712Input or output aspects

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Machine learning for syncing multiple FPGA ports in a quantum system
- Patent number 12,111,352
- Issue date Oct 8, 2024
- Quantum Machines
- Avishai Ziv
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test in a single-wire bus circuit
- Patent number 12,092,689
- Issue date Sep 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Grant
Applications of adaptive microelectronic circuits that are designed...
- Patent number 12,085,611
- Issue date Sep 10, 2024
- Minima Processor Oy
- Lauri Koskinen
- G01 - MEASURING TESTING
Information Patent Grant
Die-to-die and chip-to-chip connectivity monitoring
- Patent number 12,013,800
- Issue date Jun 18, 2024
- PROTEANTECS LTD.
- Eyal Fayneh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant analog built-in self test
- Patent number 11,996,843
- Issue date May 28, 2024
- Texas Instruments Incorporated
- Timothy Paul Duryea
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test circuit using clock gating scheme to hold capture procedure an...
- Patent number 11,959,965
- Issue date Apr 16, 2024
- Samsung Electronics Co., Ltd.
- Giha Nam
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-test for die-to-die physical interfaces
- Patent number 11,940,491
- Issue date Mar 26, 2024
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Grant
Automated test equipment for testing one or more devices under test...
- Patent number 11,913,990
- Issue date Feb 27, 2024
- Advantest Corporation
- Olaf Pöppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing a JTAG device chain in multi-die integrated circuit
- Patent number 11,675,006
- Issue date Jun 13, 2023
- Xilinx, Inc.
- Roger D. Flateau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for die-to-die physical interfaces
- Patent number 11,662,380
- Issue date May 30, 2023
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Grant
Automated hardware for input/output (I/O) test regression apparatus
- Patent number 11,604,713
- Issue date Mar 14, 2023
- International Business Machines Corporation
- Andrew C. M. Hicks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output voltage testing with boundary scan bypass
- Patent number 11,567,130
- Issue date Jan 31, 2023
- Amazon Technologies, Inc.
- Dan Trock
- G01 - MEASURING TESTING
Information Patent Grant
Support device, design support system, electrical device, and desig...
- Patent number 11,531,063
- Issue date Dec 20, 2022
- Kabushiki Kaisha Toshiba
- Tatsunori Sakano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced signaling interface circuit
- Patent number 11,519,959
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoding test data of microelectronic devices, and related methods,...
- Patent number 11,508,453
- Issue date Nov 22, 2022
- Micron Technology, Inc.
- Jason M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Display panel test circuit
- Patent number 11,493,552
- Issue date Nov 8, 2022
- SAMSUNG DISPLAY CO., LTD.
- Hwayoung Song
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Device for detecting margin of circuit operating at certain speed
- Patent number 11,488,683
- Issue date Nov 1, 2022
- Realtek Semiconductor Corporation
- Chun-Yi Kuo
- G11 - INFORMATION STORAGE
Information Patent Grant
System-on-chip for AT-SPEED test of logic circuit and operating met...
- Patent number 11,442,107
- Issue date Sep 13, 2022
- Samsung Electronics Co., Ltd.
- Beom Seok Shin
- G01 - MEASURING TESTING
Information Patent Grant
System and method for testing critical components on system-on-chip
- Patent number 11,422,185
- Issue date Aug 23, 2022
- NXP USA, INC.
- Neha Srivastava
- G01 - MEASURING TESTING
Information Patent Grant
Automated test equipment for testing one or more devices under test...
- Patent number 11,415,628
- Issue date Aug 16, 2022
- Advantest Corporation
- Olaf Pöppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated test equipment using an on-chip-system test controller
- Patent number 11,385,285
- Issue date Jul 12, 2022
- Advantest Corporation
- Olaf Pöppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan output flip-flop with power saving feature
- Patent number 11,366,162
- Issue date Jun 21, 2022
- Mediatek Inc.
- Wei-Zhe Wong
- G01 - MEASURING TESTING
Information Patent Grant
Method for characterization of standard cells with adaptive body bi...
- Patent number 11,361,800
- Issue date Jun 14, 2022
- RACYICS GMBH
- Dennis Walter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Safety circuit and method for testing a safety circuit in an automa...
- Patent number 11,353,506
- Issue date Jun 7, 2022
- WAGO Verwaltungsgesellschaft mit beschraenkter Haftung
- Alexander Buelow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chip and testing method thereof
- Patent number 11,287,472
- Issue date Mar 29, 2022
- Realtek Semiconductor Corporation
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Grant
Device monitoring using satellite ADCS having local voltage reference
- Patent number 11,199,581
- Issue date Dec 14, 2021
- Xilinx, Inc.
- John K. Jennings
- G01 - MEASURING TESTING
Information Patent Grant
Implementing a JTAG device chain in multi-die integrated circuit
- Patent number 11,199,582
- Issue date Dec 14, 2021
- Xilinx, Inc.
- Roger D. Flateau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and an apparatus for reducing the effect of local process va...
- Patent number 11,183,224
- Issue date Nov 23, 2021
- RACYICS GMBH
- Sebastian Höppner
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT
- Publication number 20240345162
- Publication date Oct 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANT ANALOG BUILT-IN SELF TEST
- Publication number 20240259023
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy Paul Duryea
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM, METHOD FOR CIRCUIT VALIDATION, AND SYSTEM AND METHOD FOR FA...
- Publication number 20240118339
- Publication date Apr 11, 2024
- SK HYNIX INC.
- YU-AN CHEN
- G01 - MEASURING TESTING
Information Patent Application
Built-in Self-Test for Die-to-Die Physical Interfaces
- Publication number 20230384377
- Publication date Nov 30, 2023
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
Machine Learning for Syncing Multiple FPGA Ports in a Quantum System
- Publication number 20230236244
- Publication date Jul 27, 2023
- Quantum Machines
- Avishai Zvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT ANALOG BUILT-IN SELF TEST
- Publication number 20230216505
- Publication date Jul 6, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Timothy Paul Duryea
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE
- Publication number 20230184830
- Publication date Jun 15, 2023
- Samsung Electronics Co., Ltd.
- Sunwook KIM
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AN...
- Publication number 20230152372
- Publication date May 18, 2023
- Samsung Electronics Co., Ltd.
- GIHA NAM
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT AND AN ELECTRONIC DEVICE INCLUDING INTEGRATED CI...
- Publication number 20230097976
- Publication date Mar 30, 2023
- Samsung Electronics Co., Ltd.
- Yeon Ho Jung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20230058458
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN SUPPORT DEVICE, DESIGN SUPPORT SYSTEM, ELECTRICAL DEVICE, AN...
- Publication number 20220221511
- Publication date Jul 14, 2022
- Kabushiki Kaisha Toshiba
- Tatsunori SAKANO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20220170983
- Publication date Jun 2, 2022
- Xilinx, Inc.
- Roger D. FLATEAU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODING TEST DATA OF MICROELECTRONIC DEVICES, AND RELATED METHODS...
- Publication number 20220059177
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Jason M. Johnson
- G01 - MEASURING TESTING
Information Patent Application
Device for detecting margin of circuit operating at certain speed
- Publication number 20220036962
- Publication date Feb 3, 2022
- REALTEK SEMICONDUCTOR CORPORATION
- CHUN-YI KUO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR TESTING CRITICAL COMPONENTS ON SYSTEM-ON-CHIP
- Publication number 20210405114
- Publication date Dec 30, 2021
- NXP USA, Inc.
- Neha Srivastava
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210325456
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN OUTPUT FLIP-FLOP WITH POWER SAVING FEATURE
- Publication number 20210325457
- Publication date Oct 21, 2021
- MEDIATEK INC.
- Wei-Zhe Wong
- G01 - MEASURING TESTING
Information Patent Application
APPLICATIONS OF ADAPTIVE MICROELECTRONIC CIRCUITS THAT ARE DESIGNED...
- Publication number 20210318377
- Publication date Oct 14, 2021
- Minima Processor Oy
- Lauri KOSKINEN
- G01 - MEASURING TESTING
Information Patent Application
IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20210311115
- Publication date Oct 7, 2021
- Xilinx, Inc.
- Roger D. FLATEAU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISPLAY PANEL TEST CIRCUIT
- Publication number 20210286002
- Publication date Sep 16, 2021
- SAMSUNG DISPLAY CO., LTD.
- HWAYOUNG SONG
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATED HARDWARE FOR INPUT/OUTPUT (I/O) TEST REGRESSION APPARATUS
- Publication number 20210248051
- Publication date Aug 12, 2021
- International Business Machines Corporation
- Andrew C. M. Hicks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...
- Publication number 20210223315
- Publication date Jul 22, 2021
- Samsung Electronics Co., Ltd.
- Beom Seok SHIN
- G01 - MEASURING TESTING
Information Patent Application
CHIP AND TESTING METHOD THEREOF
- Publication number 20210096180
- Publication date Apr 1, 2021
- REALTEK SEMICONDUCTOR CORPORATION
- Sheng-Ping YUNG
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210072310
- Publication date Mar 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED TEST EQUIPMENT FOR TESTING ONE OR MORE DEVICES UNDER TEST...
- Publication number 20210055347
- Publication date Feb 25, 2021
- Advantest Corporation
- Olaf PÖPPE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A METHOD AND AN APPARATUS FOR REDUCING THE EFFECT OF LOCAL PROCESS...
- Publication number 20200379042
- Publication date Dec 3, 2020
- RACYICS GMBH
- Sebastian HÖPPNER
- G01 - MEASURING TESTING
Information Patent Application
A METHOD AND A CIRCUIT FOR ADAPTIVE REGULATION OF BODY BIAS VOLTAGE...
- Publication number 20200379032
- Publication date Dec 3, 2020
- RACYICS GMBH
- Sebastian HÖPPNER
- G05 - CONTROLLING REGULATING
Information Patent Application
DISPLAY PANEL AND DISPLAY DEVICE
- Publication number 20200328230
- Publication date Oct 15, 2020
- BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Pengqu Zhang
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...
- Publication number 20200225284
- Publication date Jul 16, 2020
- Samsung Electronics Co., Ltd.
- Beom Seok SHIN
- G01 - MEASURING TESTING

Input or output aspects

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Machine learning for syncing multiple FPGA ports in a quantum system

Scan test in a single-wire bus circuit

Applications of adaptive microelectronic circuits that are designed...

Die-to-die and chip-to-chip connectivity monitoring

Redundant analog built-in self test

Test circuit using clock gating scheme to hold capture procedure an...

Built-in self-test for die-to-die physical interfaces

Automated test equipment for testing one or more devices under test...

Reduced signaling interface method and apparatus

Integrated circuit with reduced signaling interface

Implementing a JTAG device chain in multi-die integrated circuit

Built-in self-test for die-to-die physical interfaces

Automated hardware for input/output (I/O) test regression apparatus

Input/output voltage testing with boundary scan bypass

Support device, design support system, electrical device, and desig...

Reduced signaling interface circuit

Encoding test data of microelectronic devices, and related methods,...

Display panel test circuit

Device for detecting margin of circuit operating at certain speed

System-on-chip for AT-SPEED test of logic circuit and operating met...

System and method for testing critical components on system-on-chip

Automated test equipment for testing one or more devices under test...

Automated test equipment using an on-chip-system test controller

Scan output flip-flop with power saving feature

Method for characterization of standard cells with adaptive body bi...

Safety circuit and method for testing a safety circuit in an automa...

Chip and testing method thereof

Device monitoring using satellite ADCS having local voltage reference

Implementing a JTAG device chain in multi-die integrated circuit

Method and an apparatus for reducing the effect of local process va...

Patents Applicationslast 30 patents

SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT

REDUNDANT ANALOG BUILT-IN SELF TEST

SYSTEM, METHOD FOR CIRCUIT VALIDATION, AND SYSTEM AND METHOD FOR FA...

Built-in Self-Test for Die-to-Die Physical Interfaces

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

Machine Learning for Syncing Multiple FPGA Ports in a Quantum System

REDUNDANT ANALOG BUILT-IN SELF TEST

SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE

TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AN...

INTEGRATED CIRCUIT AND AN ELECTRONIC DEVICE INCLUDING INTEGRATED CI...

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

DESIGN SUPPORT DEVICE, DESIGN SUPPORT SYSTEM, ELECTRICAL DEVICE, AN...

IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT

ENCODING TEST DATA OF MICROELECTRONIC DEVICES, AND RELATED METHODS...

Device for detecting margin of circuit operating at certain speed

SYSTEM AND METHOD FOR TESTING CRITICAL COMPONENTS ON SYSTEM-ON-CHIP

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

SCAN OUTPUT FLIP-FLOP WITH POWER SAVING FEATURE

APPLICATIONS OF ADAPTIVE MICROELECTRONIC CIRCUITS THAT ARE DESIGNED...

IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT

DISPLAY PANEL TEST CIRCUIT

AUTOMATED HARDWARE FOR INPUT/OUTPUT (I/O) TEST REGRESSION APPARATUS

SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...

CHIP AND TESTING METHOD THEREOF

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

AUTOMATED TEST EQUIPMENT FOR TESTING ONE OR MORE DEVICES UNDER TEST...

A METHOD AND AN APPARATUS FOR REDUCING THE EFFECT OF LOCAL PROCESS...

A METHOD AND A CIRCUIT FOR ADAPTIVE REGULATION OF BODY BIAS VOLTAGE...

DISPLAY PANEL AND DISPLAY DEVICE

SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...