Interconnection testing

Industry

CPC
G01R31/31855

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31855Interconnection testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Compression-based scan test system
- Patent number 12,265,121
- Issue date Apr 1, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for testing semiconductor circuits
- Patent number 12,241,932
- Issue date Mar 4, 2025
- Ampere Computing LLC
- Kha Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital power on reset circuit and method
- Patent number 12,231,116
- Issue date Feb 18, 2025
- Ciena Corporation
- Daryl Anthony Boyd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test-time optimization with few slow scan pads
- Patent number 12,203,985
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 12,203,984
- Issue date Jan 21, 2025
- STMicroelectronics S.r.l.
- Marco Casarsa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data correction and phase optimization in high-speed receivers
- Patent number 12,181,523
- Issue date Dec 31, 2024
- Diodes Incorporated
- Yu-Wei Lin
- G01 - MEASURING TESTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Bi-directional scan flip-flop circuit and method
- Patent number 12,166,487
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Registers
- Patent number 12,158,499
- Issue date Dec 3, 2024
- Nordic Semiconductor ASA
- Matti Samuli Leinonen
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Clock gating circuits and methods for dual-edge-triggered applications
- Patent number 12,146,912
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing in a processor
- Patent number 12,140,629
- Issue date Nov 12, 2024
- Graphcore Limited
- Stephen Felix
- G01 - MEASURING TESTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable JTAG architecture for implementation of programmable...
- Patent number 12,123,912
- Issue date Oct 22, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Grant
System and method for access control of a plurality of instruments...
- Patent number 12,111,356
- Issue date Oct 8, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 12,099,090
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vehicular drawing device
- Patent number 12,095,588
- Issue date Sep 17, 2024
- Denso Corporation
- Keiya Sakamoto
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Emulation of JTAG/SCAN test interface protocols using SPI communica...
- Patent number 12,092,690
- Issue date Sep 17, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar Polasa
- G01 - MEASURING TESTING
Information Patent Grant
In system test of chips in functional systems
- Patent number 12,078,678
- Issue date Sep 3, 2024
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wrapper cell design and built-in self-test architecture for 3DIC te...
- Patent number 12,066,490
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Scan flip-flops with pre-setting combinational logic
- Patent number 12,066,489
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Grant
Integrated test circuit, test assembly and method for testing an in...
- Patent number 12,055,587
- Issue date Aug 6, 2024
- Infineon Technologies AG
- Tobias Kilian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
3D stacked die testing structure
- Patent number 12,055,586
- Issue date Aug 6, 2024
- Cadence Design Systems, Inc.
- Sagar Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test access port
- Patent number 12,050,247
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING...
- Publication number 20250116703
- Publication date Apr 10, 2025
- NXP B.V.
- Chandan Gupta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20250102569
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
- Publication number 20250096783
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Scan Data Transfer Circuits for Multi-die Chip Testing
- Publication number 20250093416
- Publication date Mar 20, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY...
- Publication number 20250085344
- Publication date Mar 13, 2025
- NXP B.V.
- CHANDAN GUPTA
- G01 - MEASURING TESTING
Information Patent Application
DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS
- Publication number 20250085345
- Publication date Mar 13, 2025
- DIODES INCORPORATED
- Yu-Wei Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20250085343
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-THROUGHPUT SCAN ARCHITECTURE
- Publication number 20250076380
- Publication date Mar 6, 2025
- Google LLC
- Syed Shakir Iqbal
- G01 - MEASURING TESTING
Information Patent Application
EYE-DIAGRAM INDEX ANALYTIC METHOD, COMPUTER READABLE RECORDING MEDI...
- Publication number 20250076379
- Publication date Mar 6, 2025
- NOVATEK MICROELECTRONICS CORP.
- Kai Li
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING
- Publication number 20250027992
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G01 - MEASURING TESTING
Information Patent Application
TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS
- Publication number 20250027994
- Publication date Jan 23, 2025
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20250027995
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
- Publication number 20240426909
- Publication date Dec 26, 2024
- SAMSUNG ELECTRONICS CO,. LTD.
- Sangsoon IM
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSION-BASED SCAN TEST SYSTEM
- Publication number 20240393393
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20240369629
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20240361384
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20240361385
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Scan Flip-Flops With Pre-Setting Combinational Logic
- Publication number 20240361383
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Application
SCAN CLOCK GATING CONTROLLER AND METHOD FOR PERFORMING STUCK-AT FAU...
- Publication number 20240353489
- Publication date Oct 24, 2024
- Realtek Semiconductor Corp.
- Dong-Zhen Li
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING MULTI-CYCLE PATHS USING SCAN TEST
- Publication number 20240329135
- Publication date Oct 3, 2024
- ADVANCED MICRO DEVICES, INC.
- James A. Wingfield
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
EMULATION OF JTAG/SCAN TEST INTERFACE PROTOCOLS USING SPI COMMUNICA...
- Publication number 20240219464
- Publication date Jul 4, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar POLASA
- G01 - MEASURING TESTING
Information Patent Application
HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE
- Publication number 20240210472
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE ACCESS PORT CIRCUITS
- Publication number 20240183903
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Interconnection testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Compression-based scan test system

Method and system for testing semiconductor circuits

Digital power on reset circuit and method

Test-time optimization with few slow scan pads

Scan chain circuit and corresponding method

Test access port with address and command capability

Integrated circuit having test circuitry for memory sub-systems

At-speed test access port operations

Data correction and phase optimization in high-speed receivers

3D tap and scan port architectures

Bi-directional scan flip-flop circuit and method

Registers

Commanded JTAG test access port operations

TVF transition coverage with self-test and production-test time red...

Clock gating circuits and methods for dual-edge-triggered applications

Scan testing in a processor

Interface to full and reduced pin JTAG devices

Reconfigurable JTAG architecture for implementation of programmable...

System and method for access control of a plurality of instruments...

Scan compression through pin data encoding

Multiplexer for SDFQ having differently-sized scan and data transis...

Vehicular drawing device

Emulation of JTAG/SCAN test interface protocols using SPI communica...

In system test of chips in functional systems

Wrapper cell design and built-in self-test architecture for 3DIC te...

Scan flip-flops with pre-setting combinational logic

Integrated test circuit, test assembly and method for testing an in...

Test access port architecture to facilitate multiple testing modes

3D stacked die testing structure

Addressable test access port

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING...

3D TAP & SCAN PORT ARCHITECTURES

BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD

Scan Data Transfer Circuits for Multi-die Chip Testing

APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY...

DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

HIGH-THROUGHPUT SCAN ARCHITECTURE

EYE-DIAGRAM INDEX ANALYTIC METHOD, COMPUTER READABLE RECORDING MEDI...

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

COMPRESSION-BASED SCAN TEST SYSTEM

ADDRESSABLE TEST ACCESS PORT

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

Scan Flip-Flops With Pre-Setting Combinational Logic

SCAN CLOCK GATING CONTROLLER AND METHOD FOR PERFORMING STUCK-AT FAU...

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

TESTING MULTI-CYCLE PATHS USING SCAN TEST

3D STACKED DIE TEST ARCHITECTURE

EMULATION OF JTAG/SCAN TEST INTERFACE PROTOCOLS USING SPI COMMUNICA...

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

MULTIPLE ACCESS PORT CIRCUITS