AUTHENTICITY AND YIELD BY READING DEFECTIVE CELLS

Abstract

Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.

Description

Claims

1. A semiconductor device, comprising: a magnetoresistive random access memory (MRAM) array comprising: defective MRAM cells comprising identified weak cells and failed cells;redundancy MRAM cells; andoperational MRAM cells;an address input electrically connected to the MRAM array; anda selector circuit wired to the address input and an output of the MRAM array, wherein the selector circuit controls a reading of the defective MRAM cells to identify the MRAM array.

2. The semiconductor device of claim 1, further comprising a defective cell address register;a redundancy cell decoder configured to enable the redundancy cells of the MRAM array; anda memory address decoder.

3. The semiconductor device of claim 2, wherein the selector circuit controls an enabling signal for the redundancy cell decoder.

4. The semiconductor device of claim 1, wherein the selector circuit comprises a multiplexer and a demultiplexer.

5. The semiconductor device of claim 4, wherein the multiplexer is electrically connected to the demultiplexer.

6. The semiconductor device of claim 1, further comprising a hash function logic block configured to output a hash value based on a reading of the defective MRAM cells.

7. The semiconductor device of claim 6, wherein the hash function logic is configured to read the defective MRAM cells to differentiate between failed MRAM cells and weak MRAM cells.

8. The semiconductor device of claim 1, wherein the selector circuit comprises: an operating mode configured to enable the redundancy cells; andan authentication mode configured to enable only the defective MRAM cells.

9. The semiconductor device of claim 1, wherein the redundancy MRAM cells are fabricated as a selection from the group consisting of: a redundancy row and a redundancy column.

10. A method of operating a semiconductor device, comprising: identifying a weak magnetoresistive random access memory (MRAM) cell of an MRAM array;identifying a failed MRAM cell of the MRAM array;identifying a redundancy MRAM cell to replace each of the weak MRAM cell and the failed MRAM cell during normal operation; andreading the weak MRAM cell and the failed MRAM cell to identify the MRAM array.

11. The method of claim 10, further comprising generating a hash value from the weak MRAM cell and the failed MRAM cell.

12. The method of claim 11, further comprising comparing the hash value to a stored hash value to determine an authenticity of the MRAM array.

13. (canceled)

14. The method of claim 10, wherein reading the weak MRAM cell and the failed MRAM cell comprises reading a signal selected from the group consisting of: a 00 signal, a 11 signal, a 01 signal, and a 10 signal.

15. The method of claim 10, wherein reading the weak MRAM cell and the failed MRAM cell comprises reading the address of the weak MRAM cell and the failed MRAM cell.

16. A method, comprising: receiving, at a selector circuit, a normal operation signal;in response to receiving the normal operation signal, enabling redundancy magnetoresistive random access memory (MRAM) cells within an MRAM array, wherein the redundancy MRAM cells are replacements for failed MRAM cells and weak MRAM cells in the MRAM array;receiving, at the selector circuit, a chip authentication signal;in response to receiving the chip authentication signal, reading the failed MRAM cells and weak MRAM cells; andidentifying the MRAM array based on the reading of the failed MRAM cells and weak MRAM cells.

17. The method of claim 16, further comprising outputting a hash value based on the reading of the weak MRAM cell and the failed MRAM cells.

18. The method of claim 16, wherein enabling the redundancy MRAM cells comprises sending a signal from the selector circuit to a redundancy cell decoder.

19. (canceled)

20. The method of claim 16, wherein reading the weak MRAM cell and the failed MRAM cell comprises reading a signal selected from the group consisting of: a 00 signal, a 11 signal, a 01 signal, and a 10 signal.