I/O lines read out arrangements

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CPC
G11C7/1069

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1069I/O lines read out arrangements

Industries

Patents Grantslast 30 patents

Information Patent Grant
Compensation for conductance drift in analog memory in crossbar array
- Patent number 12,272,422
- Issue date Apr 8, 2025
- International Business Machines Corporation
- Charles Mackin
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of operating a near memory processing-dual in-line memory m...
- Patent number 12,272,423
- Issue date Apr 8, 2025
- Samsung Electronics Co., Ltd.
- Sachin Suresh Upadhya
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller performing training to improve communication and...
- Patent number 12,272,425
- Issue date Apr 8, 2025
- SK Hynix Inc.
- Nam Hyeok Jeong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating data with stacked memory dies
- Patent number 12,265,489
- Issue date Apr 1, 2025
- Robert Nasry Hasbun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Folding ordering scheme for improved throughput in non-volatile memory
- Patent number 12,249,396
- Issue date Mar 11, 2025
- SanDisk Technologies, Inc.
- Abhinandan Venugopal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of manufacturing semiconductor device
- Patent number 12,243,618
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to perform a read of a column in a memory acce...
- Patent number 12,237,040
- Issue date Feb 25, 2025
- Intel Corporation
- Sourabh Dongaonkar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reading data from self-selecting memory, self-selecting m...
- Patent number 12,237,047
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Hwan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory device, controller for controlling the same, sto...
- Patent number 12,237,045
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Youngmin Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 12,230,359
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system
- Patent number 12,224,033
- Issue date Feb 11, 2025
- Kioxia Corporation
- Akira Katayama
- G11 - INFORMATION STORAGE
Information Patent Grant
Computing device, memory controller, and method for performing an i...
- Patent number 12,217,819
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Der Chih
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with source line control
- Patent number 12,217,822
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Perng-Fei Yuh
- G11 - INFORMATION STORAGE
Information Patent Grant
Device with client configuration and related method
- Patent number 12,210,880
- Issue date Jan 28, 2025
- STMicroelectronics S.r.l.
- Roberta Vittimani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal generator for controlling timing of signal in memory device
- Patent number 12,211,586
- Issue date Jan 28, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiu-Li Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit and method for reading data from a memory device durin...
- Patent number 12,211,570
- Issue date Jan 28, 2025
- Realtek Semiconductor Corp.
- Li-Wei Deng
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-die package
- Patent number 12,205,667
- Issue date Jan 21, 2025
- Realtek Semiconductor Corp.
- Sheng-Feng Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and operating method of memory system
- Patent number 12,205,670
- Issue date Jan 21, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Win-San Khwa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing reference currents in semiconductor devices
- Patent number 12,205,672
- Issue date Jan 21, 2025
- Macronix International Co., Ltd.
- Chun-Hsiung Hung
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller, memory system and operating method of memory system
- Patent number 12,205,662
- Issue date Jan 21, 2025
- SK Hynix Inc.
- Young Ook Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device sideband systems and methods
- Patent number 12,198,774
- Issue date Jan 14, 2025
- Micron Technology, Inc.
- Joshua E. Alzheimer
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and memory system
- Patent number 12,198,779
- Issue date Jan 14, 2025
- Kioxia Corporation
- Mitsuaki Honma
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for configuring multiple input-output channels
- Patent number 12,190,987
- Issue date Jan 7, 2025
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single port memory with multiple memory operations per clock cycle
- Patent number 12,190,994
- Issue date Jan 7, 2025
- Xilinx, Inc.
- Kumar Rahul
- G11 - INFORMATION STORAGE
Information Patent Grant
Model inversion in integrated circuit devices having analog inferen...
- Patent number 12,190,993
- Issue date Jan 7, 2025
- Micron Technology, Inc.
- Poorna Kale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and in-memory search method thereof
- Patent number 12,183,422
- Issue date Dec 31, 2024
- Macronix International Co., Ltd.
- Po-Hao Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit-cell architecture based in-memory compute
- Patent number 12,183,424
- Issue date Dec 31, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,176,062
- Issue date Dec 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- He-Zhou Wan
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory circuit and method
- Patent number 12,165,722
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Gu-Huan Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Data storage with improved cache read
- Patent number 12,165,735
- Issue date Dec 10, 2024
- SanDisk Technologies, Inc.
- Refael Ben-Rubi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM
- Publication number 20250118345
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Win-San KHWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL TIMING DRIVEN DYNAMIC VOLTAGE FREQUENCY SCALING BASED ON A...
- Publication number 20250118348
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Leon Zlotnik
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR IN-NAND PATTERN SEARCH
- Publication number 20250118368
- Publication date Apr 10, 2025
- SK HYNIX INC.
- Pengfei HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CI...
- Publication number 20250118386
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Shadden Kerstetter
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL GENERATOR FOR CONTROLLING TIMING OF SIGNAL IN MEMORY DEVICE
- Publication number 20250118346
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xiu-Li YANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME
- Publication number 20250119149
- Publication date Apr 10, 2025
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS
- Publication number 20250118343
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY AND OPERATING METHOD THEREOF
- Publication number 20250104746
- Publication date Mar 27, 2025
- GigaDevice Semiconductor Inc.
- Sibo MA
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY ARCHITECTURE
- Publication number 20250104747
- Publication date Mar 27, 2025
- STMicroelectronics International N.V.
- Alin RAZAFINDRAIBE
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY CIRCUIT AND METHOD
- Publication number 20250104785
- Publication date Mar 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Gu-Huan LI
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY AND MEMORY SYSTEM
- Publication number 20250095767
- Publication date Mar 20, 2025
- KIOXIA Corporation
- Mitsuaki HONMA
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH SPEED MEMORY CIRCUIT ARCHITECTURE WITH IMPROVED AREA AND POWER...
- Publication number 20250095698
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Sonia GHOSH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT AND OPERATION ME...
- Publication number 20250087256
- Publication date Mar 13, 2025
- Samsung Electronics Co., Ltd.
- Yoonjae Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20250078885
- Publication date Mar 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- He-Zhou WAN
- G11 - INFORMATION STORAGE
Information Patent Application
EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA
- Publication number 20250078886
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Patrick Michael Sheridan
- G11 - INFORMATION STORAGE
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20250078883
- Publication date Mar 6, 2025
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
PROCESSING IN MEMORY REGISTERS
- Publication number 20250069629
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Dmitri Yudanov
- G11 - INFORMATION STORAGE
Information Patent Application
CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALING
- Publication number 20250069632
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Leon Zlotnik
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
- Publication number 20250054526
- Publication date Feb 13, 2025
- SK HYNIX INC.
- Chan Keun KWON
- G11 - INFORMATION STORAGE
Information Patent Application
GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICES
- Publication number 20250054563
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Sehwan Park
- G11 - INFORMATION STORAGE
Information Patent Application
SKIPPING PAGES FOR WEAK WORDLINES OF A MEMORY DEVICE DURING PRE-PRO...
- Publication number 20250054527
- Publication date Feb 13, 2025
- Micron Technology, Inc.
- Cheng Cheng Ang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING THE EFFECTS OF VOLTAGE AND TEMPERATURE ON A MEMORY DEVICE...
- Publication number 20250046348
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Keun Soo Song
- G11 - INFORMATION STORAGE
Information Patent Application
REAL TIME SYNDROME CHECK
- Publication number 20250045157
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER EFFICIENT UNMATCHED DATA PATH ARCHITECTURE FOR NON-VOLATILE M...
- Publication number 20250046351
- Publication date Feb 6, 2025
- Western Digital Technologies, Inc.
- Abhishek Singhania
- G11 - INFORMATION STORAGE
Information Patent Application
DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING
- Publication number 20250046347
- Publication date Feb 6, 2025
- Lodestar Licensing Group LLC
- Peter Mayer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY READOUT CIRCUIT
- Publication number 20250037745
- Publication date Jan 30, 2025
- INFINEON TECHNOLOGIES AG
- Mihail Jefremow
- G11 - INFORMATION STORAGE
Information Patent Application
MATRIX FORMATION FOR PERFORMING COMPUTATIONAL OPERATIONS IN MEMORY
- Publication number 20250029642
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Paolo Fantini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED LOGIC GATE ACCUMULATORS
- Publication number 20250022493
- Publication date Jan 16, 2025
- Raytheon Company
- Micky R. Harris
- G11 - INFORMATION STORAGE
Information Patent Application
High-Speed and Area-Efficient Parallel-Write-and-Read Memory
- Publication number 20250022494
- Publication date Jan 16, 2025
- QUALCOMM Incorporated
- Hochul LEE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATION METHOD THEREOF
- Publication number 20250022504
- Publication date Jan 16, 2025
- Samsung Electronics Co., Ltd.
- YOON-JOO EOM
- G11 - INFORMATION STORAGE

I/O lines read out arrangements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Compensation for conductance drift in analog memory in crossbar array

Methods of operating a near memory processing-dual in-line memory m...

Memory controller performing training to improve communication and...

Communicating data with stacked memory dies

Folding ordering scheme for improved throughput in non-volatile memory

Method of manufacturing semiconductor device

Method and apparatus to perform a read of a column in a memory acce...

Method of reading data from self-selecting memory, self-selecting m...

Nonvolatile memory device, controller for controlling the same, sto...

Semiconductor device

Memory system

Computing device, memory controller, and method for performing an i...

Memory device with source line control

Device with client configuration and related method

Signal generator for controlling timing of signal in memory device

Test circuit and method for reading data from a memory device durin...

Multi-die package

Memory system and operating method of memory system

Managing reference currents in semiconductor devices

Controller, memory system and operating method of memory system

Memory device sideband systems and methods

Non-volatile memory and memory system

Method for configuring multiple input-output channels

Single port memory with multiple memory operations per clock cycle

Model inversion in integrated circuit devices having analog inferen...

Memory device and in-memory search method thereof

Bit-cell architecture based in-memory compute

Memory device

Non-volatile memory circuit and method

Data storage with improved cache read

Patents Applicationslast 30 patents

MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM

CRITICAL TIMING DRIVEN DYNAMIC VOLTAGE FREQUENCY SCALING BASED ON A...

SYSTEM AND METHOD FOR IN-NAND PATTERN SEARCH

SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CI...

SIGNAL GENERATOR FOR CONTROLLING TIMING OF SIGNAL IN MEMORY DEVICE

MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME

METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS

MEMORY AND OPERATING METHOD THEREOF

NON-VOLATILE MEMORY ARCHITECTURE

NON-VOLATILE MEMORY CIRCUIT AND METHOD

NON-VOLATILE MEMORY AND MEMORY SYSTEM

HIGH SPEED MEMORY CIRCUIT ARCHITECTURE WITH IMPROVED AREA AND POWER...

MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT AND OPERATION ME...

MEMORY DEVICE

EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

PROCESSING IN MEMORY REGISTERS

CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALING

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICES

SKIPPING PAGES FOR WEAK WORDLINES OF A MEMORY DEVICE DURING PRE-PRO...

TRACKING THE EFFECTS OF VOLTAGE AND TEMPERATURE ON A MEMORY DEVICE...

REAL TIME SYNDROME CHECK

POWER EFFICIENT UNMATCHED DATA PATH ARCHITECTURE FOR NON-VOLATILE M...

DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING

MEMORY READOUT CIRCUIT

MATRIX FORMATION FOR PERFORMING COMPUTATIONAL OPERATIONS IN MEMORY

REDUCED LOGIC GATE ACCUMULATORS

High-Speed and Area-Efficient Parallel-Write-and-Read Memory

MEMORY DEVICE AND OPERATION METHOD THEREOF