JTAG or boundary scan test of memory devices

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CPC
G01R31/318597

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318597JTAG or boundary scan test of memory devices

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Circuit and method for post-binding testing of 2.5D chiplet
- Patent number 12,188,984
- Issue date Jan 7, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial test circuit for controllable Chiplets
- Patent number 12,135,354
- Issue date Nov 5, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable JTAG architecture for implementation of programmable...
- Patent number 12,123,912
- Issue date Oct 22, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Grant
On-chip debugging device and method
- Patent number 12,085,612
- Issue date Sep 10, 2024
- Suzhou Centec Communications Co., Ltd.
- Fushan Jia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-modal memory apparatuses and systems
- Patent number 12,072,381
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die testing structure
- Patent number 12,055,586
- Issue date Aug 6, 2024
- Cadence Design Systems, Inc.
- Sagar Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Power consumption measurement assembly and method, and chip power c...
- Patent number 12,032,022
- Issue date Jul 9, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Xinwang Chen
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 12,007,441
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Interface system for interconnected die and MPU and communication m...
- Patent number 11,971,446
- Issue date Apr 30, 2024
- Jinghe Wei
- G01 - MEASURING TESTING
Information Patent Grant
Dummy dual in-line memory module (DIMM) testing system based on bou...
- Patent number 11,965,931
- Issue date Apr 23, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Yuan Sang
- G01 - MEASURING TESTING
Information Patent Grant
System on chip for performing scan test and method of designing the...
- Patent number 11,940,494
- Issue date Mar 26, 2024
- Samsung Electronics Co., Ltd.
- Woohyun Son
- G01 - MEASURING TESTING
Information Patent Grant
Flexible one-hot decoding logic for clock controls
- Patent number 11,940,493
- Issue date Mar 26, 2024
- NVIDIA Corp.
- Mahmut Yilmaz
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and system for debugging solid-state disk (SSD) device
- Patent number 11,933,847
- Issue date Mar 19, 2024
- Silicon Motion, Inc.
- Han-Chih Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for database scan acceleration
- Patent number 11,927,634
- Issue date Mar 12, 2024
- Samsung Electronics Co., Ltd.
- Andrew Chang
- G01 - MEASURING TESTING
Information Patent Grant
DIMM slot test system without series connection of test board throu...
- Patent number 11,927,632
- Issue date Mar 12, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Chang-Qing Mu
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for providing wireless FPGA programming download...
- Patent number 11,923,847
- Issue date Mar 5, 2024
- Gowin Semiconductor Corporation
- Jinghui Zhu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Baseboard management controller (BMC) test system and method
- Patent number 11,907,384
- Issue date Feb 20, 2024
- Dell Products, L.P.
- Timothy M. Lambert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug and trace circuit in lockstep architectures, associated metho...
- Patent number 11,892,505
- Issue date Feb 6, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Avneep Kumar Goyal
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus and non-transitory computer-readable storage m...
- Patent number 11,841,398
- Issue date Dec 12, 2023
- Silicon Motion, Inc.
- Yu-Lin Jiang
- G01 - MEASURING TESTING
Information Patent Grant
Memory health status reporting
- Patent number 11,775,378
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Markus Balb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test systems for executing self-testing in deployed automotive plat...
- Patent number 11,768,241
- Issue date Sep 26, 2023
- NVIDIA Corporation
- Anitha Kalva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR5 SDRAM DIMM slot detection system and method thereof
- Patent number 11,754,626
- Issue date Sep 12, 2023
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Jin-Dong Zhao
- G01 - MEASURING TESTING
Information Patent Grant
Controller for a memory component
- Patent number 11,755,350
- Issue date Sep 12, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-test circuit for an integrated circuit, and method for operati...
- Patent number 11,698,413
- Issue date Jul 11, 2023
- Infineon Technologies AG
- Juergen Alt
- G01 - MEASURING TESTING
Information Patent Grant
Falling clock edge JTAG bus routers
- Patent number 11,680,985
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor apparatus
- Patent number 11,683,883
- Issue date Jun 20, 2023
- Seiko Epson Corporation
- Yukio Okamura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D stacked die test architecture
- Patent number 11,675,007
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
JTAG bus communication method and apparatus
- Patent number 11,549,982
- Issue date Jan 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended JTAG controller and method for functional debugging using...
- Patent number 11,519,961
- Issue date Dec 6, 2022
- COMMSOLID GMBH
- Uwe Porst
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS
- Publication number 20240369631
- Publication date Nov 7, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G01 - MEASURING TESTING
Information Patent Application
MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS
- Publication number 20240369632
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM ACCESS BOUNDARY SCAN VIA SYSTEM SIDEBAND SIGNAL CONNECTIONS
- Publication number 20240288497
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Application
AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT
- Publication number 20240250668
- Publication date Jul 25, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS
- Publication number 20240125851
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- Publication number 20240120016
- Publication date Apr 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
SECURE BOOT APPARATUS AND METHOD
- Publication number 20240095366
- Publication date Mar 21, 2024
- Huawei Technologies Co., Ltd
- Jilong Ye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS
- Publication number 20240094291
- Publication date Mar 21, 2024
- NVIDIA Corp.
- Mahmut Yilmaz
- G01 - MEASURING TESTING
Information Patent Application
Multi-Partition, Multi-Domain System-on-Chip JTAG Debug Control Arc...
- Publication number 20240019494
- Publication date Jan 18, 2024
- NXP USA, Inc.
- Roderick Lee Dorris
- G01 - MEASURING TESTING
Information Patent Application
BOUNDARY SCAN FOR LIVE STATUS MONITORING
- Publication number 20230375618
- Publication date Nov 23, 2023
- B/E Aerospace, Inc.
- Hans HUIJSING
- G01 - MEASURING TESTING
Information Patent Application
SECURE JOINT TEST ACTION GROUP (JTAG)
- Publication number 20230366931
- Publication date Nov 16, 2023
- BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC
- Daniel L. Stanley
- G01 - MEASURING TESTING
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS FOR DATABASE SCAN ACCELERATION
- Publication number 20230314511
- Publication date Oct 5, 2023
- Samsung Electronics Co., Ltd.
- Andrew CHANG
- G01 - MEASURING TESTING
Information Patent Application
IN-FIELD LATENT FAULT MEMORY AND LOGIC TESTING USING STRUCTURAL TEC...
- Publication number 20230314508
- Publication date Oct 5, 2023
- Intel Corporation
- Elik Haran
- G01 - MEASURING TESTING
Information Patent Application
DDR5 SDRAM DIMM SLOT DETECTION SYSTEM AND METHOD THEREOF
- Publication number 20230296673
- Publication date Sep 21, 2023
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Jin-Dong Zhao
- G01 - MEASURING TESTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20230221368
- Publication date Jul 13, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE...
- Publication number 20230141786
- Publication date May 11, 2023
- Samsung Electronics Co., Ltd.
- WOOHYUN SON
- G01 - MEASURING TESTING
Information Patent Application
Stacked Integrated Circuit Device
- Publication number 20230116320
- Publication date Apr 13, 2023
- Graphcore Limited
- Stephen FELIX
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS AND NON-TRANSITORY COMPUTER-READABLE STORAGE M...
- Publication number 20220413047
- Publication date Dec 29, 2022
- SILICON MOTION, INC.
- Yu-Lin JIANG
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND SYSTEM FOR DEBUGGING SOLID-STATE DISK (SSD) DEVICE
- Publication number 20220413048
- Publication date Dec 29, 2022
- SILICON MOTION, INC.
- Han-Chih TSAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BASEBOARD MANAGEMENT CONTROLLER (BMC) TEST SYSTEM AND METHOD
- Publication number 20220390517
- Publication date Dec 8, 2022
- DELL PRODUCTS, L.P.
- Timothy M. Lambert
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20220381821
- Publication date Dec 1, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING THROUGH-PACKAGE DEBUG FEATURES
- Publication number 20220301952
- Publication date Sep 22, 2022
- Western Digital Technologies, Inc.
- Nir Amir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERFACE SYSTEM FOR INTERCONNECTED DIE AND MPU AND COMMUNICATION M...
- Publication number 20220276304
- Publication date Sep 1, 2022
- 58th Research Institute of China Electronics Technology Group Corporation
- Jinghe Wei
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER FOR A MEMORY COMPONENT
- Publication number 20220276885
- Publication date Sep 1, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-chip Debugging Device and Method
- Publication number 20220252665
- Publication date Aug 11, 2022
- Suzhou Centec Communications Co., Ltd.
- Fushan Jia
- G01 - MEASURING TESTING
Information Patent Application
SELF-TEST CIRCUIT FOR AN INTEGRATED CIRCUIT, AND METHOD FOR OPERATI...
- Publication number 20220107364
- Publication date Apr 7, 2022
- INFINEON TECHNOLOGIES AG
- Juergen Alt
- G01 - MEASURING TESTING
Information Patent Application
POWER CONSUMPTION MEASUREMENT ASSEMBLY AND METHOD, AND CHIP POWER C...
- Publication number 20220099741
- Publication date Mar 31, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Xinwang CHEN
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLER FOR A MEMORY COMPONENT
- Publication number 20210333327
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING

JTAG or boundary scan test of memory devices

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Circuit and method for post-binding testing of 2.5D chiplet

Commanded JTAG test access port operations

Serial test circuit for controllable Chiplets

Reconfigurable JTAG architecture for implementation of programmable...

On-chip debugging device and method

Multi-modal memory apparatuses and systems

3D stacked die testing structure

Power consumption measurement assembly and method, and chip power c...

3D stacked die test architecture

Interface system for interconnected die and MPU and communication m...

Dummy dual in-line memory module (DIMM) testing system based on bou...

System on chip for performing scan test and method of designing the...

Flexible one-hot decoding logic for clock controls

Apparatus and system for debugging solid-state disk (SSD) device

Systems and methods for database scan acceleration

DIMM slot test system without series connection of test board throu...

Method and system for providing wireless FPGA programming download...

Baseboard management controller (BMC) test system and method

Debug and trace circuit in lockstep architectures, associated metho...

Method and apparatus and non-transitory computer-readable storage m...

Memory health status reporting

Test systems for executing self-testing in deployed automotive plat...

DDR5 SDRAM DIMM slot detection system and method thereof

Controller for a memory component

Self-test circuit for an integrated circuit, and method for operati...

Falling clock edge JTAG bus routers

Semiconductor apparatus

3D stacked die test architecture

JTAG bus communication method and apparatus

Extended JTAG controller and method for functional debugging using...

Patents Applicationslast 30 patents

SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS

MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS

3D STACKED DIE TEST ARCHITECTURE

SYSTEM ACCESS BOUNDARY SCAN VIA SYSTEM SIDEBAND SIGNAL CONNECTIONS

AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT

MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS

AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES

SECURE BOOT APPARATUS AND METHOD

FLEXIBLE ONE-HOT DECODING LOGIC FOR CLOCK CONTROLS

Multi-Partition, Multi-Domain System-on-Chip JTAG Debug Control Arc...

BOUNDARY SCAN FOR LIVE STATUS MONITORING

SECURE JOINT TEST ACTION GROUP (JTAG)

FALLING CLOCK EDGE JTAG BUS ROUTERS

SYSTEMS AND METHODS FOR DATABASE SCAN ACCELERATION

IN-FIELD LATENT FAULT MEMORY AND LOGIC TESTING USING STRUCTURAL TEC...

DDR5 SDRAM DIMM SLOT DETECTION SYSTEM AND METHOD THEREOF

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE...

Stacked Integrated Circuit Device

METHOD AND APPARATUS AND NON-TRANSITORY COMPUTER-READABLE STORAGE M...

APPARATUS AND SYSTEM FOR DEBUGGING SOLID-STATE DISK (SSD) DEVICE

BASEBOARD MANAGEMENT CONTROLLER (BMC) TEST SYSTEM AND METHOD

3D STACKED DIE TEST ARCHITECTURE

SEMICONDUCTOR DEVICE INCLUDING THROUGH-PACKAGE DEBUG FEATURES

INTERFACE SYSTEM FOR INTERCONNECTED DIE AND MPU AND COMMUNICATION M...

CONTROLLER FOR A MEMORY COMPONENT

On-chip Debugging Device and Method

SELF-TEST CIRCUIT FOR AN INTEGRATED CIRCUIT, AND METHOD FOR OPERATI...

POWER CONSUMPTION MEASUREMENT ASSEMBLY AND METHOD, AND CHIP POWER C...

CONTROLLER FOR A MEMORY COMPONENT