Macro blocks

Industry

CPC
H03K19/17732

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Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K19/00Logic circuits

Current Industry

H03K19/17732Macro blocks

Industries

Patents Grantslast 30 patents

Information Patent Grant
Process of routing tile-to-tile interconnects of an FPGA, and metho...
- Patent number 11,916,551
- Issue date Feb 27, 2024
- Flex Logix Technologies, Inc.
- Yongning Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid synchronous and asynchronous control for scan-based testing
- Patent number 11,755,804
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for remote field programmable gate array proce...
- Patent number 11,675,326
- Issue date Jun 13, 2023
- Intel Corporation
- Nicolas A. Salhuana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing block with reduced pin count for fine-gra...
- Patent number 11,356,101
- Issue date Jun 7, 2022
- EFINIX, INC.
- Ho Man Ho
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hierarchical sort/merge structure using a request pipe
- Patent number 11,354,094
- Issue date Jun 7, 2022
- International Business Machines Corporation
- Norbert Hagspiel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridged integrated circuits
- Patent number 11,283,451
- Issue date Mar 22, 2022
- Google LLC
- Jonathan Ross
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process of routing tile-to-tile interconnects of an FPGA, and metho...
- Patent number 11,277,135
- Issue date Mar 15, 2022
- Flex Logix Technologies, Inc.
- Yongning Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for remote field programmable gate array proce...
- Patent number 11,029,659
- Issue date Jun 8, 2021
- Intel Corporation
- Nicolas A. Salhuana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer size optimization in a hierarchical structure
- Patent number 10,936,283
- Issue date Mar 2, 2021
- International Business Machines Corporation
- Norbert Hagspiel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridged integrated circuits
- Patent number 10,886,923
- Issue date Jan 5, 2021
- Google LLC
- Jonathan Ross
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process of routing tile-to-tile interconnects of an FPGA, and metho...
- Patent number 10,855,284
- Issue date Dec 1, 2020
- Flex Logix Technologies, Inc.
- Yongning Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable first in first out and deserializer circuitry
- Patent number 10,771,063
- Issue date Sep 8, 2020
- Intel Corporation
- Eah Loon Alan Chuah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic integrated circuit, design support system, and c...
- Patent number 10,740,435
- Issue date Aug 11, 2020
- NEC Corporation
- Noboru Sakimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication operations in memory
- Patent number 10,705,798
- Issue date Jul 7, 2020
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridged integrated circuits
- Patent number 10,637,478
- Issue date Apr 28, 2020
- Jonathan Ross
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable logic array
- Patent number 10,425,081
- Issue date Sep 24, 2019
- Hitachi, Ltd.
- Teruaki Sakata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication operations in memory
- Patent number 10,409,555
- Issue date Sep 10, 2019
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for and method of accessing memory elements in an integrate...
- Patent number 10,396,799
- Issue date Aug 27, 2019
- Xilinx, Inc.
- Vishwak R Manda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bridged integrated circuits
- Patent number 10,374,608
- Issue date Aug 6, 2019
- Jonathan Ross
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for configurable interface and associated methods
- Patent number 10,270,447
- Issue date Apr 23, 2019
- Altera Corporation
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable object array having image processing circuitry
- Patent number 10,182,236
- Issue date Jan 15, 2019
- Nytell Software LLC
- Dean Stuart Susnow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Virtual FPGA management and optimization system
- Patent number 10,164,639
- Issue date Dec 25, 2018
- Advanced Micro Devices, Inc.
- David A. Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic circuit including dynamic lookup table
- Patent number 9,966,960
- Issue date May 8, 2018
- Silicon Laboratories Inc.
- Alan Lee Westwick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit device with programmable analog subsystem
- Patent number 9,960,773
- Issue date May 1, 2018
- Cypress Semiconductor Corporation
- Eashwar Thiagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplication operations in memory
- Patent number 9,904,515
- Issue date Feb 27, 2018
- Micron Technology, Inc.
- Sanjay Tiwari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple-layer configuration storage for runtime reconfigurable sys...
- Patent number 9,853,644
- Issue date Dec 26, 2017
- FutureWei Technologies, Inc.
- Qiang Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient constant multiplier implementation for programmable logic...
- Patent number 9,841,945
- Issue date Dec 12, 2017
- Lattice Semiconductor Corporation
- Sunil Kumar Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array with integrated application specific...
- Patent number 9,705,506
- Issue date Jul 11, 2017
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable object array having image processing circuitry
- Patent number 9,648,345
- Issue date May 9, 2017
- Nytell Software LLC
- Dean Stuart Susnow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple-layer configuration storage for runtime reconfigurable sys...
- Patent number 9,503,096
- Issue date Nov 22, 2016
- FutureWei Technologies, Inc.
- Qiang Wang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
RECONFIGURABLE ARRAY FOR ANALOG APPLICATIONS
- Publication number 20230344431
- Publication date Oct 26, 2023
- Drexel University
- Ioannis Savidis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Process of Routing Tile-to-Tile Interconnects of an FPGA, and Metho...
- Publication number 20220173738
- Publication date Jun 2, 2022
- Flex Logix Technologies, Inc.
- Yongning Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR REMOTE FIELD PROGRAMMABLE GATE ARRAY PROCE...
- Publication number 20210294292
- Publication date Sep 23, 2021
- Intel Corporation
- Nicolas A. Salhuana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process of Routing Tile-to-Tile Interconnects of an FPGA, and Metho...
- Publication number 20210083674
- Publication date Mar 18, 2021
- Flex Logix Technologies, Inc.
- Yongning Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLICATION OPERATIONS IN MEMORY
- Publication number 20190391789
- Publication date Dec 26, 2019
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable First In First Out and Deserializer Circuitry
- Publication number 20190319628
- Publication date Oct 17, 2019
- Intel Corporation
- Eah Loon Alan Chuah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FIELD PROGRAMMABLE OBJECT ARRAY HAVING IMAGE PROCESSING CIRCUITRY
- Publication number 20180295374
- Publication date Oct 11, 2018
- NYTELL SOFTWARE LLC
- Dean Stuart Susnow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS
- Publication number 20180212607
- Publication date Jul 26, 2018
- KABUSHIKI KAISHA TOSHIBA
- Masato ODA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM
- Publication number 20170085268
- Publication date Mar 23, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Eashwar Thiagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable Logic Circuit Including Dynamic Lookup Table
- Publication number 20160182054
- Publication date Jun 23, 2016
- Silicon Laboratories Inc.
- Alan Lee Westwick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADAPTIVE INTERFACE FOR COUPLING FPGA MODULES
- Publication number 20140333344
- Publication date Nov 13, 2014
- dSpace digital signal processing and control engineering GmbH
- Dirk HASSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20140210515
- Publication date Jul 31, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURABLE EMBEDDED MEMORY SYSTEM
- Publication number 20140133246
- Publication date May 15, 2014
- Xilinx, Inc.
- Subodh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20140082035
- Publication date Mar 20, 2014
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20130332497
- Publication date Dec 12, 2013
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20130214815
- Publication date Aug 22, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configuration Context Switcher with a Latch
- Publication number 20130162291
- Publication date Jun 27, 2013
- Tabula, Inc.
- Martin Voogel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION CONTEXT SWITCHER
- Publication number 20130147514
- Publication date Jun 13, 2013
- Tabula, Inc.
- Trevis Chandler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRA...
- Publication number 20130117504
- Publication date May 9, 2013
- Xilinx, Inc.
- Christopher E. Neely
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC...
- Publication number 20130009666
- Publication date Jan 10, 2013
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20120217998
- Publication date Aug 30, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURATION CONTEXT SWITCHER WITH A CLOCKED STORAGE ELEMENT
- Publication number 20120187979
- Publication date Jul 26, 2012
- Trevis Chandler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adjustable Interface Buffer Circuit Between A Programmable Logic De...
- Publication number 20110298492
- Publication date Dec 8, 2011
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMMUNICATION WITHIN AN INTEGRATED CIRCUIT INCLUDING AN ARRAY OF IN...
- Publication number 20110268137
- Publication date Nov 3, 2011
- Stephen John Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURATION CONTEXT SWITCHER WITH A LATCH
- Publication number 20110254586
- Publication date Oct 20, 2011
- Martin Voogel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED FILED PROGRAMMABLE GATE ARRAY
- Publication number 20110234258
- Publication date Sep 29, 2011
- Actel Corporation
- Samuel W. Beal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURATION CONTEXT SWITCHER
- Publication number 20110089970
- Publication date Apr 21, 2011
- Tabula, Inc.
- Trevis Chandler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable field device for use in process automation systems
- Publication number 20110035576
- Publication date Feb 10, 2011
- Endress + Hauser GmbH + Co.KG
- Udo Grittke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System for the flexible configuration of functional modules
- Publication number 20110025376
- Publication date Feb 3, 2011
- Endress + Hauser GmbH + Co.KG
- Udo Grittke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Field device for determining and monitoring process variable in pro...
- Publication number 20110029254
- Publication date Feb 3, 2011
- Endress + Hauser GmbH + Co.KG
- Udo Grittke
- H03 - BASIC ELECTRONIC CIRCUITRY

Macro blocks

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Process of routing tile-to-tile interconnects of an FPGA, and metho...

Hybrid synchronous and asynchronous control for scan-based testing

Method and apparatus for remote field programmable gate array proce...

Digital signal processing block with reduced pin count for fine-gra...

Hierarchical sort/merge structure using a request pipe

Bridged integrated circuits

Process of routing tile-to-tile interconnects of an FPGA, and metho...

Method and apparatus for remote field programmable gate array proce...

Buffer size optimization in a hierarchical structure

Bridged integrated circuits

Process of routing tile-to-tile interconnects of an FPGA, and metho...

Configurable first in first out and deserializer circuitry

Programmable logic integrated circuit, design support system, and c...

Multiplication operations in memory

Bridged integrated circuits

Field programmable logic array

Multiplication operations in memory

Circuit for and method of accessing memory elements in an integrate...

Bridged integrated circuits

Apparatus for configurable interface and associated methods

Field programmable object array having image processing circuitry

Virtual FPGA management and optimization system

Configurable logic circuit including dynamic lookup table

Integrated circuit device with programmable analog subsystem

Multiplication operations in memory

Multiple-layer configuration storage for runtime reconfigurable sys...

Efficient constant multiplier implementation for programmable logic...

Field programmable gate array with integrated application specific...

Field programmable object array having image processing circuitry

Multiple-layer configuration storage for runtime reconfigurable sys...

Patents Applicationslast 30 patents

RECONFIGURABLE ARRAY FOR ANALOG APPLICATIONS

Process of Routing Tile-to-Tile Interconnects of an FPGA, and Metho...

METHOD AND APPARATUS FOR REMOTE FIELD PROGRAMMABLE GATE ARRAY PROCE...

Process of Routing Tile-to-Tile Interconnects of an FPGA, and Metho...

MULTIPLICATION OPERATIONS IN MEMORY

Configurable First In First Out and Deserializer Circuitry

FIELD PROGRAMMABLE OBJECT ARRAY HAVING IMAGE PROCESSING CIRCUITRY

INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS

INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM

Configurable Logic Circuit Including Dynamic Lookup Table

ADAPTIVE INTERFACE FOR COUPLING FPGA MODULES

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

CONFIGURABLE EMBEDDED MEMORY SYSTEM

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Configuration Context Switcher with a Latch

CONFIGURATION CONTEXT SWITCHER

EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRA...

FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC...

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

CONFIGURATION CONTEXT SWITCHER WITH A CLOCKED STORAGE ELEMENT

Adjustable Interface Buffer Circuit Between A Programmable Logic De...

COMMUNICATION WITHIN AN INTEGRATED CIRCUIT INCLUDING AN ARRAY OF IN...

CONFIGURATION CONTEXT SWITCHER WITH A LATCH

ENHANCED FILED PROGRAMMABLE GATE ARRAY

CONFIGURATION CONTEXT SWITCHER

Configurable field device for use in process automation systems

System for the flexible configuration of functional modules

Field device for determining and monitoring process variable in pro...