Manipulation of word size

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GPHYSICS G11Information storage G11CSTATIC STORES

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G11C2029/1804Manipulation of word size

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Patents Grantslast 30 patents

Information Patent Grant
Variable page size architecture
- Patent number 11,961,588
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline capacitance balancing
- Patent number 11,948,651
- Issue date Apr 2, 2024
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Grant
ECC in integrated memory assembly
- Patent number 11,482,296
- Issue date Oct 25, 2022
- SanDisk Technologies LLC
- Idan Alrod
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline capacitance balancing
- Patent number 11,462,289
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable page size architecture
- Patent number 11,244,713
- Issue date Feb 8, 2022
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline capacitance balancing
- Patent number 10,998,074
- Issue date May 4, 2021
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory with match hit quality indication
- Patent number 10,614,884
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable page size architecture
- Patent number 10,566,040
- Issue date Feb 18, 2020
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory with match hit quality indication
- Patent number 10,347,337
- Issue date Jul 9, 2019
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory integrity
- Patent number 9,847,872
- Issue date Dec 19, 2017
- Intel Corporation
- David M. Durham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor memory device
- Patent number 9,607,686
- Issue date Mar 28, 2017
- Kabushiki Kaisha Toshiba
- Yukihiro Fujimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction coding over multiple memory pages
- Patent number 9,136,879
- Issue date Sep 15, 2015
- Apple Inc.
- Micha Anholt
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction coding over multiple memory pages
- Patent number 8,495,465
- Issue date Jul 23, 2013
- Apple Inc.
- Micha Anholt
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory and method for testing the same
- Patent number 8,433,960
- Issue date Apr 30, 2013
- Fujitsu Semiconductor Limited
- Kaoru Mori
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory and method for testing the same
- Patent number 8,276,027
- Issue date Sep 25, 2012
- Fujitsu Semiconductor Limited
- Kaoru Mori
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip and semiconductor device using the memory chip and manu...
- Patent number 7,977,159
- Issue date Jul 12, 2011
- Kabushiki Kaisha Toshiba
- Yukihiro Urakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory and method for testing the same
- Patent number 7,937,630
- Issue date May 3, 2011
- Fujitsu Semiconductor Limited
- Kaoru Mori
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and method for testing the same
- Patent number 7,872,940
- Issue date Jan 18, 2011
- Hynix Semiconductor Inc.
- Ki Chang Kwean
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip on chip device including basic chips capable of functioning in...
- Patent number 7,466,029
- Issue date Dec 16, 2008
- Kabushiki Kaisha Toshiba
- Yukihiro Urakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device testable with a single data rate and/or...
- Patent number 7,454,672
- Issue date Nov 18, 2008
- Samsung Electronics Co., Ltd.
- Jong-Cheol Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory-module board layout for use with memory chips of different d...
- Patent number 7,414,312
- Issue date Aug 19, 2008
- Kingston Technology Corp.
- Henry H. D. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for separating native, functional and test con...
- Patent number 7,260,700
- Issue date Aug 21, 2007
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device capable of changing data output mode
- Patent number 7,126,864
- Issue date Oct 24, 2006
- Hynix Semiconductor, Inc.
- Jun Seop Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including parallel test circuit
- Patent number 7,126,865
- Issue date Oct 24, 2006
- Hynix Semiconductor Inc.
- Yun Seok Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods for changing page length in a semiconductor me...
- Patent number 6,868,034
- Issue date Mar 15, 2005
- Samsung Electronics Co., Ltd.
- One-Gyun La
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip and semiconductor device using the memory chip and manu...
- Patent number 6,737,743
- Issue date May 18, 2004
- Kabushiki Kaisha Toshiba
- Yukihiro Urakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 6,650,582
- Issue date Nov 18, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Junko Matsumoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device having improvement arrangem...
- Patent number 5,587,607
- Issue date Dec 24, 1996
- Mitsubishi Denki Kabushiki Kaisha
- Kenichi Yasuda
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
VARIABLE PAGE SIZE ARCHITECTURE
- Publication number 20240347088
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE CAPACITANCE BALANCING
- Publication number 20230031126
- Publication date Feb 2, 2023
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Application
ECC IN INTEGRATED MEMORY ASSEMBLY
- Publication number 20210383886
- Publication date Dec 9, 2021
- SANDISK TECHNOLOGIES LLC
- Idan Alrod
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE CAPACITANCE BALANCING
- Publication number 20210335436
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE CAPACITANCE BALANCING
- Publication number 20210027852
- Publication date Jan 28, 2021
- Micron Technology, Inc.
- Corrado Villa
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY WITH MATCH HIT QUALITY INDICATION
- Publication number 20190206492
- Publication date Jul 4, 2019
- International Business Machines Corporation
- Martin ECKERT
- G11 - INFORMATION STORAGE
Information Patent Application
Error Correction Coding Over Multiple Memory Pages
- Publication number 20130283122
- Publication date Oct 24, 2013
- Micha Anholt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME
- Publication number 20120057420
- Publication date Mar 8, 2012
- FUJITSU SEMICONDUCTOR LIMITED
- Kaoru MORI
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME
- Publication number 20110167307
- Publication date Jul 7, 2011
- FUJITSU SEMICONDUCTOR LIMITED
- Kaoru MORI
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device and method for testing the same
- Publication number 20090154271
- Publication date Jun 18, 2009
- Hynix Semiconductor Inc.
- Ki-Chang Kwean
- G11 - INFORMATION STORAGE
Information Patent Application
Memory test circuit
- Publication number 20080222460
- Publication date Sep 11, 2008
- QIMONDA NORTH AMERICA CORP.
- Jaehee Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Memory testing system and method
- Publication number 20080163013
- Publication date Jul 3, 2008
- Robert James Landers
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory and method for testing the same
- Publication number 20070268762
- Publication date Nov 22, 2007
- FUJITSU LIMITED
- Kaoru Mori
- G11 - INFORMATION STORAGE
Information Patent Application
Memory-Module Board Layout for Use With Memory Chips of Different D...
- Publication number 20060267172
- Publication date Nov 30, 2006
- KINGSTON TECHNOLOGY CORP.
- Henry H.D. Nguyen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Memory having a portion that can be switched between use as data an...
- Publication number 20060218467
- Publication date Sep 28, 2006
- James M. Sibigtroth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory chip and semiconductor device using the memory chip and manu...
- Publication number 20060148130
- Publication date Jul 6, 2006
- Yukihiro Urakawa
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device capable of changing data output mode
- Publication number 20060109724
- Publication date May 25, 2006
- Hynix Semiconductor Inc.
- Jun Seop Chung
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for separating native, functional and test con...
- Publication number 20060085701
- Publication date Apr 20, 2006
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device including parallel test circuit
- Publication number 20050195666
- Publication date Sep 8, 2005
- Hynix Semiconductor Inc.
- Yun Seok Hong
- G11 - INFORMATION STORAGE
Information Patent Application
Memory chip and semiconductor device using the memory chip and manu...
- Publication number 20040164425
- Publication date Aug 26, 2004
- Yukihiro Urakawa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device testable with a single data rate and/or...
- Publication number 20040151039
- Publication date Aug 5, 2004
- SAMSUNG ELECTRONICS CO., LTD.
- Jong-Cheol Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Circuits and methods for changing page length in a semiconductor me...
- Publication number 20040095835
- Publication date May 20, 2004
- One-Gyun La
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20030081479
- Publication date May 1, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Junko Matsumoto
- G11 - INFORMATION STORAGE
Information Patent Application
Memory chip and semiconductor device using the memory chip and manu...
- Publication number 20030015792
- Publication date Jan 23, 2003
- Yukihiro Urakawa
- H01 - BASIC ELECTRIC ELEMENTS

Manipulation of word size

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Variable page size architecture

Wordline capacitance balancing

ECC in integrated memory assembly

Wordline capacitance balancing

Variable page size architecture

Wordline capacitance balancing

Content addressable memory with match hit quality indication

Variable page size architecture

Content addressable memory with match hit quality indication

Memory integrity

Semiconductor memory device

Error correction coding over multiple memory pages

Error correction coding over multiple memory pages

Semiconductor memory and method for testing the same

Semiconductor memory and method for testing the same

Memory chip and semiconductor device using the memory chip and manu...

Semiconductor memory and method for testing the same

Semiconductor memory device and method for testing the same

Chip on chip device including basic chips capable of functioning in...

Semiconductor memory device testable with a single data rate and/or...

Memory-module board layout for use with memory chips of different d...

Method and apparatus for separating native, functional and test con...

Memory device capable of changing data output mode

Memory device including parallel test circuit

Circuits and methods for changing page length in a semiconductor me...

Memory chip and semiconductor device using the memory chip and manu...

Semiconductor memory device

Semiconductor integrated circuit device having improvement arrangem...

Patents Applicationslast 30 patents

VARIABLE PAGE SIZE ARCHITECTURE

WORDLINE CAPACITANCE BALANCING

ECC IN INTEGRATED MEMORY ASSEMBLY

WORDLINE CAPACITANCE BALANCING

WORDLINE CAPACITANCE BALANCING

CONTENT ADDRESSABLE MEMORY WITH MATCH HIT QUALITY INDICATION

Error Correction Coding Over Multiple Memory Pages

SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME

SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME

Semiconductor memory device and method for testing the same

Memory test circuit

Memory testing system and method

Semiconductor memory and method for testing the same

Memory-Module Board Layout for Use With Memory Chips of Different D...

Memory having a portion that can be switched between use as data an...

Memory chip and semiconductor device using the memory chip and manu...

Memory device capable of changing data output mode

Method and apparatus for separating native, functional and test con...

Memory device including parallel test circuit

Memory chip and semiconductor device using the memory chip and manu...

Semiconductor memory device testable with a single data rate and/or...

Circuits and methods for changing page length in a semiconductor me...

Semiconductor memory device

Memory chip and semiconductor device using the memory chip and manu...