The present invention relates generally to data storage, and particularly to methods and systems for error correction coding in memory systems.
Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Memory systems often apply Error Correction Coding (ECC) techniques to the stored data in order to increase storage reliability and reduce the likelihood of readout errors. For example, U.S. Patent Application Publication 2009/0013233, whose disclosure is incorporated herein by reference, describes apparatus and methods for storing error recovery data in different dimensions of a memory array. In example embodiments, in one dimension, block error correction codes are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.
As another example, U.S. Patent Application Publication 2010/0169743, whose disclosure is incorporated herein by reference, describes a solid state disk that includes a non-volatile memory and a controller. The controller performs ECC on data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data.
An embodiment of the present invention that is described herein provides a method for data storage, including:
encoding each of multiple data items individually using a first Error Correction Code (ECC) to produce respective encoded data items, and storing the encoded data items in a memory;
encoding the multiple data items jointly using a second ECC, so as to produce a code word of the second ECC, and storing only a part of the code word in the memory;
recalling the stored encoded data items from the memory and decoding the first ECC in order to reconstruct the data items; and
upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, reconstructing the given data item based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item.
In some embodiments, the code word of the second ECC includes data bits and redundancy bits, and the part of the code word includes only the redundancy bits of the code word. In an embodiment, encoding the multiple data items using the second ECC includes calculating a bitwise Exclusive OR (XOR) over the multiple data items, and applying the second ECC to the bitwise XOR. In a disclosed embodiment, reconstructing the given data item includes calculating an interim bitwise XOR over the given data item and over the decoded and reconstructed data items other than the given data item, decoding the second ECC for an interim code word including the interim bitwise XOR and the stored redundancy bits, and deriving the given data item from the decoded interim code word and the decoded and reconstructed data items other than the given data item.
In some embodiments, the first ECC has a first error correction capability, and the second ECC has a second error correction capability that is greater than the first error correction capability. In an embodiment, the method includes, upon failing to reconstruct two or more data items from the respective encoded data items by decoding the first ECC, re-attempting to reconstruct the two or more data items by decoding the first ECC using an erasure decoding process.
In another embodiment, reconstructing the given data item includes reconstructing the code word of the second ECC and decoding the reconstructed code word. In yet another embodiment, the second ECC is represented by a set of parity check equations, and decoding the code word includes simplifying one or more of the parity check equations in the set based on the reconstructed data items other than the given data item, and decoding the code word using the simplified parity check equations. In still another embodiment, the first ECC is represented by an additional set of parity check equations, and decoding the code word includes, after simplifying the parity check equations in the set, jointly decoding the parity check equations of the first ECC and of the second ECC. In an embodiment, the second ECC includes a Low Density Parity Check (LDPC) code.
There is additionally provided, in accordance with an embodiment of the present invention, a data storage apparatus, including:
an interface, which is configured to communicate with a memory; and
a processing unit, which is configured to encode each of multiple data items individually using a first Error Correction Code (ECC) so as to produce respective encoded data items, to store the encoded data items in the memory, to encode the multiple data items jointly using a second ECC so as to produce a code word of the second ECC, to store only a part of the code word in the memory, to recall the stored encoded data items from the memory and decode the first ECC in order to reconstruct the data items, and, upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, to reconstruct the given data item based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:
Embodiments of the present invention that are described hereinbelow provide improved methods and devices for data storage. In some embodiments, a memory controller stores multiple data pages in a memory. The memory controller encodes the data of each memory page individually with an Error Correction Code (ECC) denoted ECC1, and stores the encoded pages in the memory. In order to retrieve the data, the memory controller reads the encoded pages from the memory and decodes ECC1.
Sometimes, however, a given page comprises a number of errors that exceeds the correction capability of ECC1, and therefore the memory controller will most likely fail to decode ECC1 for this page. In some practical cases, when considering a group of N pages, the likeliest situation is that all except one of the pages are decodable, and no more than one page has an exceedingly high number of errors.
In some embodiments, the memory controller handles such scenarios by encoding the data of the N pages jointly using an additional ECC, denoted ECC2. Encoding the N pages using ECC2 produces a single code word, which comprises data bits and redundancy bits. The memory controller stores only part of the ECC2 code word, typically only the redundancy bits of the code word and not the data bits, in the memory. (As will be explained in detail below, the data bits of the ECC2 code word are superfluous when the N−1 pages other than the failed page are decodable.)
During data retrieval, if the memory controller fails to decode ECC1 for a given page out of the N pages, it reconstructs the data of the failed page using (1) the stored part (e.g., redundancy bits) of the ECC2 code word, and (2) the decoded data of the N−1 pages other than the failed page. Since the memory controller stores only the redundancy bits of the ECC2 code word, not the entire code word, the storage overhead used by the disclosed techniques is small.
The disclosed techniques enable the memory controller to fully reconstruct the data of the N pages, even though ECC1 is not decodable for one page. Under certain circumstances, the disclosed techniques can also be applied even when ECC1 is not decodable for more than a single page.
In some embodiments, the memory controller produces the ECC2 code word by calculating a bitwise Exclusive OR (XOR) over the N pages, and then encoding the XOR result using ECC2. In alternative embodiments, the memory controller applies certain types of ECC2, e.g., a Low Density Parity Check (LDPC) code, directly to the data of the N pages. Decoding schemes for both options are described herein.
System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array may comprise solid-state analog memory cells of any kind, such as, for example, NAND, NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory—PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells. Although the embodiments described herein refer mainly to analog memory, the disclosed techniques can also be used with various other memory types.
The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values, storage values or analog storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.
System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values into the cell.
Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to analog storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W unit can erase a group of cells 32 by applying one or more negative erasure pulses to the cells.
The storage and retrieval of data in and out of memory device 24 is performed by a memory controller 40. Memory controller 40 comprises an interface 44 for communicating with memory device 24, and an Error Correction Coding (ECC) unit 48. ECC unit 48 encodes the data for storage with an ECC and decodes the ECC of data that is read from memory, using methods that are described in detail below.
Memory controller 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. Memory controller 40, and in particular unit 48, may be implemented in hardware, e.g., using one or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs). Alternatively, the memory controller may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.
The configuration of
In the exemplary system configuration shown in
In some embodiments, memory controller 40 comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.
In an example configuration of array 28, memory cells 32 are arranged in multiple rows and columns, and each memory cell comprises a floating-gate transistor. The gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. The memory array is typically divided into multiple memory pages, i.e., groups of memory cells that are programmed and read simultaneously.
Memory pages are sometimes sub-divided into sectors. In some embodiments, each page occupies an entire row of the array, i.e., an entire word line. For two-bit-per-cell devices, for example, each word line stores two pages. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In an example implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row.
Erasing of cells is usually carried out in blocks that contain multiple pages. Typical memory devices may comprise thousands of erasure blocks. In a typical two-bit-per-cell MLC device, each erasure block is on the order of 32 word lines, each comprising several tens of thousands of cells. Each word line of such a device is often partitioned into four pages (odd/even order cells, least/most significant bit of the cells). Three-bit-per cell devices having 32 word lines per erasure block would have 192 pages per erasure block, and four-bit-per-cell devices would have 256 pages per block. Alternatively, other block sizes and configurations can also be used. Some memory devices comprise two or more separate memory cell arrays, often referred to as planes. Since each plane has a certain “busy” period between successive write operations, data can be written alternately to the different planes in order to increase programming speed.
In some embodiments, memory controller 40 encodes the data of each memory page individually with a certain ECC, and stores the encoded pages in memory device 24. The ECC may comprise, for example, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Low Density Parity Check (LDPC) code or any other suitable type of ECC. When retrieving data from memory device 24, the memory controller reads encoded pages from the memory, decodes the ECC and outputs the decoded data.
Sometimes, however, memory controller 40 may fail in decoding the ECC of a given encoded page, because the number of errors in that page exceeds the correction capability of the ECC. In some cases, the errors are not distributed evenly among the encoded pages, e.g., because of distortion or variations in the quality of the storage media between different physical locations in the memory. In these scenarios, most pages may be decoded successfully, whereas one or few pages suffer from an exceedingly high number of errors. Embodiments of the present invention that are described herein provide improved storage methods and devices, which increase storage reliability by encoding the stored data with additional redundancy that is computed jointly over multiple pages.
In some embodiments, memory controller 40 stores certain data in device 24 in N memory pages, after encoding the data of each page individually with a certain ECC (referred to herein as ECC1). In addition, the memory controller encodes the data of all N pages jointly using a second ECC denoted ECC2. The latter encoding operation produces a single code word of ECC2, which comprises data bits and redundancy bits. The memory controller stores only the redundancy bits (and not the data bits) of the ECC2 code word in device 24. When retrieving the data from device 24, memory controller reads the N encoded pages from the memory and attempts to decode ECC1 for each page. If ECC1 decoding fails for a given encoded page out of the N encoded pages, the memory controller reconstructs the failed page based on (1) the redundancy bits of the ECC2 code word, and (2) the N−1 pages other than the failed page.
ECC1 has a certain error correction capability, i.e., a maximum number of errors that can be corrected. If the actual number of errors in a certain page exceeds the error correction capability of ECC1, memory controller 40 will fail in decoding ECC1 for that page. In some scenarios, N−1 out of the N pages are decodable without errors, and only a single page cannot be recovered by decoding ECC1.
In order to recover the data reliably in the presence of such failure scenarios, memory controller 40 applies an additional encoding scheme, referred to as ECC2. Although the embodiments described herein refer mainly to recovery of a single failed page out of N pages, some of the disclosed techniques can also be used to recover two or more failed pages, as will be explained further below.
In the example of
When retrieving the N pages, memory controller 40 reads the N encoded pages from memory device 24, and attempts to decode ECC1 for each page. If ECC1 fails to decode for a certain page, the memory controller retrieves redundancy information 72 (i.e., the redundancy bits of the ECC2 code word) from memory device 24. The memory controller then reconstructs the data of the failed page using redundancy information 72 and the N−1 successfully-decoded pages.
Memory controller 40 encodes the data of the N pages using ECC2 so as to produce a single code word, and stores the redundancy bits of this code word in memory device 24, at an ECC2 storage step 88. In the present example, the memory controller calculates a bitwise XOR over the (un-encoded) data of the N pages, encodes the resulting bitwise XOR page using ECC2, and then stores the redundancy bits of the resulting ECC2 code word.
At a later point in time, memory controller 40 is requested to retrieve the data stored in the N pages. In order to retrieve the data, the memory controller reads the N pages from memory device 24 and attempts to decode ECC1 for each page, at a initial readout step 92. The memory controller checks whether ECC1 decoding is successful for all N pages, at a decoding checking step 96. If ECC1 was decoded successfully for all N pages, memory controller 40 outputs the decoded data to the host, at a success termination step 100, and the method terminates.
If ECC1 was not successful for all N pages, the memory controller checks whether only a single page has failed ECC1 decoding, at a single page checking step 104. If more than a single page failed ECC1 decoding, the memory controller outputs the decoded data of only the successfully-decoded pages, at a partial success termination step 108, and the method terminates. Alternatively, the memory controller may report failure without outputting any decoded data.
If only a single page out of the N pages has failed ECC1 decoding, the memory controller carries out a process that reconstructs the data of the failed page based on the redundancy bits of the ECC2 code word and on the data of the N−1 successfully-decoded pages. First, the memory controller calculates a bitwise XOR over the N pages, at a XOR calculation step 112. The bitwise XOR at this stage is calculated over the decoded data of the N−1 successfully-decoded pages, as well as the data read from the failed page (the raw data read from memory, not the result of the unsuccessful ECC1 decoding operation).
The memory controller reads the ECC2 redundancy bits (stored at step 88 above) from memory, and uses it to reconstruct the original bitwise XOR (that was computed but not stored at step 88 above), at a XOR reconstruction step 116. In the present example, the memory controller constructs an ECC2 code word, whose data bits are the bitwise XOR calculated at step 112 above, and whose redundancy bits are the ECC2 redundancy bits read from memory. The result of this ECC2 decoding operation is the original bitwise XOR that was calculated but not stored at step 88 above.
The memory controller reconstructs the data of the failed page using the original bitwise XOR derived at step 116, at a failed page reconstruction step 120. Typically, the memory controller subtracts (bitwise) a bitwise XOR of the N−1 successfully-decoded pages from the original bitwise XOR derived at step 116. The subtraction result comprises the data of the failed page. The memory controller then outputs the data of the N pages, at success termination step 100, and the method terminates.
Note that the result obtained at step 120 is correct assuming ECC2 is decoded without errors. For this purpose, ECC2 is typically designed to have a higher error correction capability than ECC1.
In an example embodiment, each page is 2K bits in size, ECC1 comprises a BCH code with a correction capability of thirty errors per code word (T=30), ECC2 comprises another BCH code with a correction capability of sixty errors per code word (T=60), and ECC2 is calculated over twenty-four pages. Alternatively, however, any other suitable configuration can also be used.
In some embodiments, the method described above can be used to recover from ECC1 decoding failure in two (and possibly more) pages out of the N pages, assuming ECC2 was decoded successfully at step 116. In an example embodiment, the memory controller detects that ECC1 decoding has failed for two pages. In this event, the memory controller re-attempts to decode ECC1 for the two pages in question, this time using erasure decoding. Since erasure decoding is typically able to correct a higher number of errors, the erasure decoding has some likelihood of decoding one of the failed pages successfully. If the erasure decoding attempt is successful (and thus only one page has remaining errors), the method of
In the embodiments described above, the memory controller calculates a bitwise XOR over the N pages data and then encodes the XOR result using ECC2. In alternative embodiments, the memory controller can apply ECC2 directly to the data of the N pages. In these embodiments, after successful decoding of ECC1 in all but one page, the decoded data of the N−1 successfully-decoded pages can be used to simplify one or more of the parity check equations of ECC2. The equations can be simplified by removing some of their variables, which correspond to bits that are known through the ECC1 decoding. As a result, decoding of ECC2 can be simplified considerably, thus reducing latency and power consumption.
In these embodiments, ECC2 has a much larger block size, which is equal to the number of bits in all N pages. In an example embodiment of this sort ECC2 comprises an LDPC code, although any other suitable ECC can also be used. This technique is especially suitable for LDPC, since this type of code can be decoded using the same decoder after removing some of the code word bits (some of the columns in the code's parity check matrix). In some embodiments, the parity check equations of ECC2 (after removing the variables that correspond to known bits) are joined with the parity check equations of ECC1, such that the resulting code has a higher correction capability than ECC2 alone. The memory controller then decodes this joint ECC by evaluating the parity check equations of ECC1 and ECC2 jointly.
Although the embodiments described herein mainly address memory pages, the techniques described herein can also be used with any other suitable data items that may be encoded individually with ECC1, such as sectors or word lines. Although the embodiments described herein mainly address encoding and decoding in memory systems, the methods and systems described herein can also be used in other applications, such as in communication systems. In communication applications, the pages referred to herein are replaced by ECC frames, each of which may comprise a packet or part of a packet, for example.
It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.
This application claims the benefit of U.S. Provisional Patent Application 61/251,807, filed Oct. 15, 2009, whose disclosure is incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
3668631 | Griffith et al. | Jun 1972 | A |
3668632 | Oldham | Jun 1972 | A |
4058851 | Scheuneman | Nov 1977 | A |
4112502 | Scheuneman | Sep 1978 | A |
4394763 | Nagano et al. | Jul 1983 | A |
4413339 | Riggle et al. | Nov 1983 | A |
4556961 | Iwahashi et al. | Dec 1985 | A |
4558431 | Satoh | Dec 1985 | A |
4608687 | Dutton | Aug 1986 | A |
4654847 | Dutton | Mar 1987 | A |
4661929 | Aoki et al. | Apr 1987 | A |
4768171 | Tada | Aug 1988 | A |
4811285 | Walker et al. | Mar 1989 | A |
4899342 | Potter et al. | Feb 1990 | A |
4910706 | Hyatt | Mar 1990 | A |
4993029 | Galbraith et al. | Feb 1991 | A |
5056089 | Furuta et al. | Oct 1991 | A |
5077722 | Geist et al. | Dec 1991 | A |
5126808 | Montalvo et al. | Jun 1992 | A |
5163021 | Mehrotra et al. | Nov 1992 | A |
5172338 | Mehrotra et al. | Dec 1992 | A |
5182558 | Mayo | Jan 1993 | A |
5182752 | DeRoo et al. | Jan 1993 | A |
5191584 | Anderson | Mar 1993 | A |
5200959 | Gross et al. | Apr 1993 | A |
5237535 | Mielke et al. | Aug 1993 | A |
5272669 | Samachisa et al. | Dec 1993 | A |
5276649 | Hoshita et al. | Jan 1994 | A |
5287469 | Tsuboi | Feb 1994 | A |
5365484 | Cleveland et al. | Nov 1994 | A |
5388064 | Khan | Feb 1995 | A |
5416646 | Shirai | May 1995 | A |
5416782 | Wells et al. | May 1995 | A |
5446854 | Khalidi et al. | Aug 1995 | A |
5450424 | Okugaki et al. | Sep 1995 | A |
5469444 | Endoh et al. | Nov 1995 | A |
5473753 | Wells et al. | Dec 1995 | A |
5479170 | Cauwenberghs et al. | Dec 1995 | A |
5508958 | Fazio et al. | Apr 1996 | A |
5519831 | Holzhammer | May 1996 | A |
5532962 | Auclair et al. | Jul 1996 | A |
5533190 | Binford et al. | Jul 1996 | A |
5541886 | Hasbun | Jul 1996 | A |
5600677 | Citta et al. | Feb 1997 | A |
5638320 | Wong et al. | Jun 1997 | A |
5657332 | Auclair et al. | Aug 1997 | A |
5675540 | Roohparvar | Oct 1997 | A |
5682352 | Wong et al. | Oct 1997 | A |
5687114 | Khan | Nov 1997 | A |
5696717 | Koh | Dec 1997 | A |
5726649 | Tamaru et al. | Mar 1998 | A |
5726934 | Tran et al. | Mar 1998 | A |
5742752 | De Koning | Apr 1998 | A |
5748533 | Dunlap et al. | May 1998 | A |
5748534 | Dunlap et al. | May 1998 | A |
5751637 | Chen et al. | May 1998 | A |
5761402 | Kaneda et al. | Jun 1998 | A |
5798966 | Keeney | Aug 1998 | A |
5799200 | Brant et al. | Aug 1998 | A |
5801985 | Roohparvar et al. | Sep 1998 | A |
5838832 | Barnsley | Nov 1998 | A |
5860106 | Domen et al. | Jan 1999 | A |
5867114 | Barbir | Feb 1999 | A |
5867428 | Ishii et al. | Feb 1999 | A |
5867429 | Chen et al. | Feb 1999 | A |
5877986 | Harari et al. | Mar 1999 | A |
5889937 | Tamagawa | Mar 1999 | A |
5901089 | Korsh et al. | May 1999 | A |
5909449 | So et al. | Jun 1999 | A |
5912906 | Wu et al. | Jun 1999 | A |
5930167 | Lee et al. | Jul 1999 | A |
5937424 | Leak et al. | Aug 1999 | A |
5942004 | Cappelletti | Aug 1999 | A |
5946716 | Karp et al. | Aug 1999 | A |
5969986 | Wong et al. | Oct 1999 | A |
5982668 | Ishii et al. | Nov 1999 | A |
5991517 | Harari et al. | Nov 1999 | A |
5995417 | Chen et al. | Nov 1999 | A |
6009014 | Hollmer et al. | Dec 1999 | A |
6009016 | Ishii et al. | Dec 1999 | A |
6023425 | Ishii et al. | Feb 2000 | A |
6034891 | Norman | Mar 2000 | A |
6040993 | Chen et al. | Mar 2000 | A |
6041430 | Yamauchi | Mar 2000 | A |
6073204 | Lakhani et al. | Jun 2000 | A |
6101614 | Gonzales et al. | Aug 2000 | A |
6128237 | Shirley et al. | Oct 2000 | A |
6134140 | Tanaka et al. | Oct 2000 | A |
6134143 | Norman | Oct 2000 | A |
6134631 | Jennings | Oct 2000 | A |
6141261 | Patti | Oct 2000 | A |
6151246 | So et al. | Nov 2000 | A |
6157573 | Ishii et al. | Dec 2000 | A |
6166962 | Chen et al. | Dec 2000 | A |
6169691 | Pasotti et al. | Jan 2001 | B1 |
6178466 | Gilbertson et al. | Jan 2001 | B1 |
6185134 | Tanaka et al. | Feb 2001 | B1 |
6209113 | Roohparvar | Mar 2001 | B1 |
6212654 | Lou et al. | Apr 2001 | B1 |
6219276 | Parker | Apr 2001 | B1 |
6219447 | Lee et al. | Apr 2001 | B1 |
6222762 | Guterman et al. | Apr 2001 | B1 |
6230233 | Lofgren et al. | May 2001 | B1 |
6240458 | Gilbertson | May 2001 | B1 |
6259627 | Wong | Jul 2001 | B1 |
6275419 | Guterman et al. | Aug 2001 | B1 |
6278632 | Chevallier | Aug 2001 | B1 |
6279069 | Robinson et al. | Aug 2001 | B1 |
6288944 | Kawamura | Sep 2001 | B1 |
6292394 | Cohen et al. | Sep 2001 | B1 |
6301151 | Engh et al. | Oct 2001 | B1 |
6304486 | Yano | Oct 2001 | B1 |
6307776 | So et al. | Oct 2001 | B1 |
6314044 | Sasaki et al. | Nov 2001 | B1 |
6317363 | Guterman et al. | Nov 2001 | B1 |
6317364 | Guterman et al. | Nov 2001 | B1 |
6345004 | Omura et al. | Feb 2002 | B1 |
6360346 | Miyauchi et al. | Mar 2002 | B1 |
6363008 | Wong | Mar 2002 | B1 |
6363454 | Lakhani et al. | Mar 2002 | B1 |
6366496 | Torelli et al. | Apr 2002 | B1 |
6385092 | Ishii et al. | May 2002 | B1 |
6392932 | Ishii et al. | May 2002 | B1 |
6396742 | Korsh et al. | May 2002 | B1 |
6397364 | Barkan | May 2002 | B1 |
6405323 | Lin et al. | Jun 2002 | B1 |
6405342 | Lee | Jun 2002 | B1 |
6418060 | Yang et al. | Jul 2002 | B1 |
6442585 | Dean et al. | Aug 2002 | B1 |
6445602 | Kokudo et al. | Sep 2002 | B1 |
6452838 | Ishii et al. | Sep 2002 | B1 |
6456528 | Chen | Sep 2002 | B1 |
6466476 | Wong et al. | Oct 2002 | B1 |
6467062 | Barkan | Oct 2002 | B1 |
6469931 | Ban et al. | Oct 2002 | B1 |
6480948 | Virajpet et al. | Nov 2002 | B1 |
6490236 | Fukuda et al. | Dec 2002 | B1 |
6522580 | Chen et al. | Feb 2003 | B2 |
6525952 | Araki et al. | Feb 2003 | B2 |
6532556 | Wong et al. | Mar 2003 | B1 |
6538922 | Khalid et al. | Mar 2003 | B1 |
6549464 | Tanaka et al. | Apr 2003 | B2 |
6553510 | Pekny et al. | Apr 2003 | B1 |
6558967 | Wong | May 2003 | B1 |
6560152 | Cernea | May 2003 | B1 |
6567311 | Ishii et al. | May 2003 | B2 |
6577539 | Iwahashi | Jun 2003 | B2 |
6584012 | Banks | Jun 2003 | B2 |
6615307 | Roohparvar | Sep 2003 | B1 |
6621739 | Gonzalez et al. | Sep 2003 | B2 |
6640326 | Buckingham et al. | Oct 2003 | B1 |
6643169 | Rudelic et al. | Nov 2003 | B2 |
6646913 | Micheloni et al. | Nov 2003 | B2 |
6678192 | Gongwer et al. | Jan 2004 | B2 |
6683811 | Ishii et al. | Jan 2004 | B2 |
6687155 | Nagasue | Feb 2004 | B2 |
6707748 | Lin et al. | Mar 2004 | B2 |
6708257 | Bao | Mar 2004 | B2 |
6714449 | Khalid | Mar 2004 | B2 |
6717847 | Chen | Apr 2004 | B2 |
6731557 | Beretta | May 2004 | B2 |
6732250 | Durrant | May 2004 | B2 |
6738293 | Iwahashi | May 2004 | B1 |
6751766 | Guterman et al. | Jun 2004 | B2 |
6757193 | Chen et al. | Jun 2004 | B2 |
6774808 | Hibbs et al. | Aug 2004 | B1 |
6781877 | Cernea et al. | Aug 2004 | B2 |
6804805 | Rub | Oct 2004 | B2 |
6807095 | Chen et al. | Oct 2004 | B2 |
6807101 | Ooishi et al. | Oct 2004 | B2 |
6809964 | Moschopoulos et al. | Oct 2004 | B2 |
6819592 | Noguchi et al. | Nov 2004 | B2 |
6829167 | Tu et al. | Dec 2004 | B2 |
6845052 | Ho et al. | Jan 2005 | B1 |
6851018 | Wyatt et al. | Feb 2005 | B2 |
6851081 | Yamamoto | Feb 2005 | B2 |
6856546 | Guterman et al. | Feb 2005 | B2 |
6862218 | Guterman et al. | Mar 2005 | B2 |
6870767 | Rudelic et al. | Mar 2005 | B2 |
6870773 | Noguchi et al. | Mar 2005 | B2 |
6873552 | Ishii et al. | Mar 2005 | B2 |
6879520 | Hosono et al. | Apr 2005 | B2 |
6882567 | Wong | Apr 2005 | B1 |
6894926 | Guterman et al. | May 2005 | B2 |
6907497 | Hosono et al. | Jun 2005 | B2 |
6925009 | Noguchi et al. | Aug 2005 | B2 |
6930925 | Guo et al. | Aug 2005 | B2 |
6934188 | Roohparvar | Aug 2005 | B2 |
6937511 | Hsu et al. | Aug 2005 | B2 |
6958938 | Noguchi et al. | Oct 2005 | B2 |
6963505 | Cohen | Nov 2005 | B2 |
6972993 | Conley et al. | Dec 2005 | B2 |
6988175 | Lasser | Jan 2006 | B2 |
6992932 | Cohen | Jan 2006 | B2 |
6999344 | Hosono et al. | Feb 2006 | B2 |
7002843 | Guterman et al. | Feb 2006 | B2 |
7006379 | Noguchi et al. | Feb 2006 | B2 |
7012835 | Gonzalez et al. | Mar 2006 | B2 |
7020017 | Chen et al. | Mar 2006 | B2 |
7023735 | Ban et al. | Apr 2006 | B2 |
7031210 | Park et al. | Apr 2006 | B2 |
7031214 | Tran | Apr 2006 | B2 |
7031216 | You | Apr 2006 | B2 |
7039846 | Hewitt et al. | May 2006 | B2 |
7042766 | Wang et al. | May 2006 | B1 |
7054193 | Wong | May 2006 | B1 |
7054199 | Lee et al. | May 2006 | B2 |
7057958 | So et al. | Jun 2006 | B2 |
7065147 | Ophir et al. | Jun 2006 | B2 |
7068539 | Guterman et al. | Jun 2006 | B2 |
7071849 | Zhang | Jul 2006 | B2 |
7072222 | Ishii et al. | Jul 2006 | B2 |
7079555 | Baydar et al. | Jul 2006 | B2 |
7088615 | Guterman et al. | Aug 2006 | B2 |
7099194 | Tu et al. | Aug 2006 | B2 |
7102924 | Chen et al. | Sep 2006 | B2 |
7113432 | Mokhlesi | Sep 2006 | B2 |
7130210 | Bathul et al. | Oct 2006 | B2 |
7139192 | Wong | Nov 2006 | B1 |
7139198 | Guterman et al. | Nov 2006 | B2 |
7145805 | Ishii et al. | Dec 2006 | B2 |
7151692 | Wu | Dec 2006 | B2 |
7158058 | Yu | Jan 2007 | B1 |
7170781 | So et al. | Jan 2007 | B2 |
7170802 | Cernea et al. | Jan 2007 | B2 |
7173859 | Hemink | Feb 2007 | B2 |
7177184 | Chen | Feb 2007 | B2 |
7177195 | Gonzalez et al. | Feb 2007 | B2 |
7177199 | Chen et al. | Feb 2007 | B2 |
7177200 | Ronen et al. | Feb 2007 | B2 |
7184338 | Nakagawa et al. | Feb 2007 | B2 |
7187195 | Kim | Mar 2007 | B2 |
7187592 | Guterman et al. | Mar 2007 | B2 |
7190614 | Wu | Mar 2007 | B2 |
7193898 | Cernea | Mar 2007 | B2 |
7193921 | Choi et al. | Mar 2007 | B2 |
7196644 | Anderson et al. | Mar 2007 | B1 |
7196928 | Chen | Mar 2007 | B2 |
7196933 | Shibata | Mar 2007 | B2 |
7197594 | Raz et al. | Mar 2007 | B2 |
7200062 | Kinsely et al. | Apr 2007 | B2 |
7210077 | Brandenberger et al. | Apr 2007 | B2 |
7221592 | Nazarian | May 2007 | B2 |
7224613 | Chen et al. | May 2007 | B2 |
7231474 | Helms et al. | Jun 2007 | B1 |
7231562 | Ohlhoff et al. | Jun 2007 | B2 |
7243275 | Gongwer et al. | Jul 2007 | B2 |
7254690 | Rao | Aug 2007 | B2 |
7254763 | Aadsen et al. | Aug 2007 | B2 |
7257027 | Park | Aug 2007 | B2 |
7259987 | Chen et al. | Aug 2007 | B2 |
7266026 | Gongwer et al. | Sep 2007 | B2 |
7266069 | Chu | Sep 2007 | B2 |
7269066 | Nguyen et al. | Sep 2007 | B2 |
7272757 | Stocken | Sep 2007 | B2 |
7274611 | Roohparvar | Sep 2007 | B2 |
7277355 | Tanzawa | Oct 2007 | B2 |
7280398 | Lee | Oct 2007 | B1 |
7280409 | Misumi et al. | Oct 2007 | B2 |
7280415 | Hwang et al. | Oct 2007 | B2 |
7283399 | Ishii et al. | Oct 2007 | B2 |
7289344 | Chen | Oct 2007 | B2 |
7301807 | Khalid et al. | Nov 2007 | B2 |
7301817 | Li et al. | Nov 2007 | B2 |
7308525 | Lasser et al. | Dec 2007 | B2 |
7310255 | Chan | Dec 2007 | B2 |
7310269 | Shibata | Dec 2007 | B2 |
7310271 | Lee | Dec 2007 | B2 |
7310272 | Mokhesi et al. | Dec 2007 | B1 |
7310347 | Lasser | Dec 2007 | B2 |
7312727 | Feng et al. | Dec 2007 | B1 |
7321509 | Chen et al. | Jan 2008 | B2 |
7328384 | Kulkarni et al. | Feb 2008 | B1 |
7342831 | Mokhlesi et al. | Mar 2008 | B2 |
7343330 | Boesjes et al. | Mar 2008 | B1 |
7345924 | Nguyen et al. | Mar 2008 | B2 |
7345928 | Li | Mar 2008 | B2 |
7349263 | Kim et al. | Mar 2008 | B2 |
7356755 | Fackenthal | Apr 2008 | B2 |
7363420 | Lin et al. | Apr 2008 | B2 |
7365671 | Anderson | Apr 2008 | B1 |
7388781 | Litsyn et al. | Jun 2008 | B2 |
7397697 | So et al. | Jul 2008 | B2 |
7405974 | Yaoi et al. | Jul 2008 | B2 |
7405979 | Ishii et al. | Jul 2008 | B2 |
7408804 | Hemink et al. | Aug 2008 | B2 |
7408810 | Aritome et al. | Aug 2008 | B2 |
7409473 | Conley et al. | Aug 2008 | B2 |
7409623 | Baker et al. | Aug 2008 | B2 |
7420847 | Li | Sep 2008 | B2 |
7433231 | Aritome | Oct 2008 | B2 |
7433697 | Karaoguz et al. | Oct 2008 | B2 |
7434111 | Sugiura et al. | Oct 2008 | B2 |
7437498 | Ronen | Oct 2008 | B2 |
7440324 | Mokhlesi | Oct 2008 | B2 |
7440331 | Hemink | Oct 2008 | B2 |
7441067 | Gorobets et al. | Oct 2008 | B2 |
7447970 | Wu et al. | Nov 2008 | B2 |
7450421 | Mokhlesi et al. | Nov 2008 | B2 |
7453737 | Ha | Nov 2008 | B2 |
7457163 | Hemink | Nov 2008 | B2 |
7457897 | Lee et al. | Nov 2008 | B1 |
7460410 | Nagai et al. | Dec 2008 | B2 |
7460412 | Lee et al. | Dec 2008 | B2 |
7466592 | Mitani et al. | Dec 2008 | B2 |
7468907 | Kang et al. | Dec 2008 | B2 |
7468911 | Lutze et al. | Dec 2008 | B2 |
7469049 | Feng | Dec 2008 | B1 |
7471581 | Tran et al. | Dec 2008 | B2 |
7483319 | Brown | Jan 2009 | B2 |
7487329 | Hepkin et al. | Feb 2009 | B2 |
7487394 | Forhan et al. | Feb 2009 | B2 |
7492641 | Hosono et al. | Feb 2009 | B2 |
7508710 | Mokhlesi | Mar 2009 | B2 |
7526711 | Orio | Apr 2009 | B2 |
7539061 | Lee | May 2009 | B2 |
7539062 | Doyle | May 2009 | B2 |
7551492 | Kim | Jun 2009 | B2 |
7558109 | Brandman et al. | Jul 2009 | B2 |
7558839 | McGovern | Jul 2009 | B1 |
7568135 | Cornwell et al. | Jul 2009 | B2 |
7570520 | Kamei et al. | Aug 2009 | B2 |
7574555 | Porat et al. | Aug 2009 | B2 |
7590002 | Mokhlesi et al. | Sep 2009 | B2 |
7593259 | Kim | Sep 2009 | B2 |
7594093 | Kancherla | Sep 2009 | B1 |
7596707 | Vemula | Sep 2009 | B1 |
7609787 | Jahan et al. | Oct 2009 | B2 |
7613043 | Cornwell et al. | Nov 2009 | B2 |
7616498 | Mokhlesi et al. | Nov 2009 | B2 |
7619918 | Aritome | Nov 2009 | B2 |
7631245 | Lasser | Dec 2009 | B2 |
7633798 | Sarin et al. | Dec 2009 | B2 |
7633802 | Mokhlesi | Dec 2009 | B2 |
7639532 | Roohparvar et al. | Dec 2009 | B2 |
7644347 | Alexander et al. | Jan 2010 | B2 |
7656734 | Thorp et al. | Feb 2010 | B2 |
7660158 | Aritome | Feb 2010 | B2 |
7660183 | Ware et al. | Feb 2010 | B2 |
7661000 | Ueda et al. | Feb 2010 | B2 |
7661054 | Huffman et al. | Feb 2010 | B2 |
7665007 | Yang et al. | Feb 2010 | B2 |
7680987 | Clark et al. | Mar 2010 | B1 |
7733712 | Walston et al. | Jun 2010 | B1 |
7742351 | Inoue et al. | Jun 2010 | B2 |
7761624 | Karamcheti et al. | Jul 2010 | B2 |
7797609 | Neuman | Sep 2010 | B2 |
7810017 | Radke | Oct 2010 | B2 |
7848149 | Gonzalez et al. | Dec 2010 | B2 |
7869273 | Lee et al. | Jan 2011 | B2 |
7885119 | Li | Feb 2011 | B2 |
7904783 | Brandman et al. | Mar 2011 | B2 |
7928497 | Yaegashi | Apr 2011 | B2 |
7929549 | Talbot | Apr 2011 | B1 |
7930515 | Gupta et al. | Apr 2011 | B2 |
7945825 | Cohen et al. | May 2011 | B2 |
7978516 | Olbrich et al. | Jul 2011 | B2 |
8014094 | Jin | Sep 2011 | B1 |
8037380 | Cagno et al. | Oct 2011 | B2 |
8040744 | Gorobets et al. | Oct 2011 | B2 |
8065583 | Radke | Nov 2011 | B2 |
20010002172 | Tanaka et al. | May 2001 | A1 |
20010006479 | Ikehashi et al. | Jul 2001 | A1 |
20020038440 | Barkan | Mar 2002 | A1 |
20020056064 | Kidorf et al. | May 2002 | A1 |
20020118574 | Gongwer et al. | Aug 2002 | A1 |
20020133684 | Anderson | Sep 2002 | A1 |
20020166091 | Kidorf et al. | Nov 2002 | A1 |
20020174295 | Ulrich et al. | Nov 2002 | A1 |
20020196510 | Hietala et al. | Dec 2002 | A1 |
20030002348 | Chen et al. | Jan 2003 | A1 |
20030103400 | Van Tran | Jun 2003 | A1 |
20030161183 | Van Tran | Aug 2003 | A1 |
20030189856 | Cho et al. | Oct 2003 | A1 |
20040057265 | Mirabel et al. | Mar 2004 | A1 |
20040057285 | Cernea et al. | Mar 2004 | A1 |
20040083333 | Chang et al. | Apr 2004 | A1 |
20040083334 | Chang et al. | Apr 2004 | A1 |
20040105311 | Cernea et al. | Jun 2004 | A1 |
20040114437 | Li | Jun 2004 | A1 |
20040160842 | Fukiage | Aug 2004 | A1 |
20040223371 | Roohparvar | Nov 2004 | A1 |
20050007802 | Gerpheide | Jan 2005 | A1 |
20050013165 | Ban | Jan 2005 | A1 |
20050024941 | Lasser et al. | Feb 2005 | A1 |
20050024978 | Ronen | Feb 2005 | A1 |
20050030788 | Parkinson et al. | Feb 2005 | A1 |
20050086574 | Fackenthal | Apr 2005 | A1 |
20050121436 | Kamitani et al. | Jun 2005 | A1 |
20050144361 | Gonzalez et al. | Jun 2005 | A1 |
20050157555 | Ono et al. | Jul 2005 | A1 |
20050162913 | Chen | Jul 2005 | A1 |
20050169051 | Khalid et al. | Aug 2005 | A1 |
20050189649 | Maruyama et al. | Sep 2005 | A1 |
20050213393 | Lasser | Sep 2005 | A1 |
20050224853 | Ohkawa | Oct 2005 | A1 |
20050240745 | Iyer et al. | Oct 2005 | A1 |
20050243626 | Ronen | Nov 2005 | A1 |
20060004952 | Lasser | Jan 2006 | A1 |
20060028875 | Avraham et al. | Feb 2006 | A1 |
20060028877 | Meir | Feb 2006 | A1 |
20060101193 | Murin | May 2006 | A1 |
20060106972 | Gorobets et al. | May 2006 | A1 |
20060107136 | Gongwer et al. | May 2006 | A1 |
20060129750 | Lee et al. | Jun 2006 | A1 |
20060133141 | Gorobets | Jun 2006 | A1 |
20060156189 | Tomlin | Jul 2006 | A1 |
20060179334 | Brittain et al. | Aug 2006 | A1 |
20060190699 | Lee | Aug 2006 | A1 |
20060203546 | Lasser | Sep 2006 | A1 |
20060218359 | Sanders et al. | Sep 2006 | A1 |
20060221692 | Chen | Oct 2006 | A1 |
20060221705 | Hemink et al. | Oct 2006 | A1 |
20060221714 | Li et al. | Oct 2006 | A1 |
20060239077 | Park et al. | Oct 2006 | A1 |
20060239081 | Roohparvar | Oct 2006 | A1 |
20060256620 | Nguyen et al. | Nov 2006 | A1 |
20060256626 | Werner et al. | Nov 2006 | A1 |
20060256891 | Yuan et al. | Nov 2006 | A1 |
20060271748 | Jain et al. | Nov 2006 | A1 |
20060285392 | Incarnati et al. | Dec 2006 | A1 |
20060285396 | Ha | Dec 2006 | A1 |
20070006013 | Moshayedi et al. | Jan 2007 | A1 |
20070019481 | Park | Jan 2007 | A1 |
20070033581 | Tomlin et al. | Feb 2007 | A1 |
20070047314 | Goda et al. | Mar 2007 | A1 |
20070047326 | Nguyen et al. | Mar 2007 | A1 |
20070050536 | Kolokowsky | Mar 2007 | A1 |
20070058446 | Hwang et al. | Mar 2007 | A1 |
20070061502 | Lasser et al. | Mar 2007 | A1 |
20070067667 | Ikeuchi et al. | Mar 2007 | A1 |
20070074093 | Lasser | Mar 2007 | A1 |
20070086239 | Litsyn et al. | Apr 2007 | A1 |
20070086260 | Sinclair | Apr 2007 | A1 |
20070089034 | Litsyn et al. | Apr 2007 | A1 |
20070091677 | Lasser et al. | Apr 2007 | A1 |
20070091694 | Lee et al. | Apr 2007 | A1 |
20070103978 | Conley et al. | May 2007 | A1 |
20070103986 | Chen | May 2007 | A1 |
20070104211 | Opsasnick | May 2007 | A1 |
20070109845 | Chen | May 2007 | A1 |
20070109849 | Chen | May 2007 | A1 |
20070115726 | Cohen et al. | May 2007 | A1 |
20070118713 | Guterman et al. | May 2007 | A1 |
20070143378 | Gorobetz | Jun 2007 | A1 |
20070143531 | Atri | Jun 2007 | A1 |
20070159889 | Kang et al. | Jul 2007 | A1 |
20070159892 | Kang et al. | Jul 2007 | A1 |
20070159907 | Kwak | Jul 2007 | A1 |
20070168837 | Murin | Jul 2007 | A1 |
20070171714 | Wu et al. | Jul 2007 | A1 |
20070183210 | Choi et al. | Aug 2007 | A1 |
20070189073 | Aritome | Aug 2007 | A1 |
20070195602 | Fong et al. | Aug 2007 | A1 |
20070206426 | Mokhlesi | Sep 2007 | A1 |
20070208904 | Hsieh et al. | Sep 2007 | A1 |
20070226599 | Motwani | Sep 2007 | A1 |
20070236990 | Aritome | Oct 2007 | A1 |
20070253249 | Kang et al. | Nov 2007 | A1 |
20070256620 | Viggiano et al. | Nov 2007 | A1 |
20070263455 | Cornwell et al. | Nov 2007 | A1 |
20070266232 | Rodgers et al. | Nov 2007 | A1 |
20070271424 | Lee et al. | Nov 2007 | A1 |
20070280000 | Fujiu et al. | Dec 2007 | A1 |
20070291571 | Balasundaram | Dec 2007 | A1 |
20070297234 | Cernea et al. | Dec 2007 | A1 |
20080010395 | Mylly et al. | Jan 2008 | A1 |
20080016428 | Lee et al. | Jan 2008 | A1 |
20080025121 | Tanzawa | Jan 2008 | A1 |
20080043535 | Roohparvar | Feb 2008 | A1 |
20080049504 | Kasahara et al. | Feb 2008 | A1 |
20080049506 | Guterman | Feb 2008 | A1 |
20080052446 | Lasser et al. | Feb 2008 | A1 |
20080055993 | Lee | Mar 2008 | A1 |
20080080243 | Edahiro et al. | Apr 2008 | A1 |
20080082730 | Kim et al. | Apr 2008 | A1 |
20080089123 | Chae et al. | Apr 2008 | A1 |
20080104309 | Cheon et al. | May 2008 | A1 |
20080104312 | Lasser | May 2008 | A1 |
20080109590 | Jung et al. | May 2008 | A1 |
20080115017 | Jacobson | May 2008 | A1 |
20080123420 | Brandman et al. | May 2008 | A1 |
20080123426 | Lutze et al. | May 2008 | A1 |
20080126686 | Sokolov et al. | May 2008 | A1 |
20080130341 | Shalvi et al. | Jun 2008 | A1 |
20080148115 | Sokolov et al. | Jun 2008 | A1 |
20080151618 | Sharon et al. | Jun 2008 | A1 |
20080151667 | Miu et al. | Jun 2008 | A1 |
20080158958 | Sokolov et al. | Jul 2008 | A1 |
20080181001 | Shalvi | Jul 2008 | A1 |
20080198650 | Shalvi et al. | Aug 2008 | A1 |
20080198654 | Toda | Aug 2008 | A1 |
20080209116 | Caulkins | Aug 2008 | A1 |
20080209304 | Winarski et al. | Aug 2008 | A1 |
20080215798 | Sharon et al. | Sep 2008 | A1 |
20080219050 | Shalvi et al. | Sep 2008 | A1 |
20080239093 | Easwar et al. | Oct 2008 | A1 |
20080239812 | Abiko et al. | Oct 2008 | A1 |
20080253188 | Aritome | Oct 2008 | A1 |
20080263262 | Sokolov et al. | Oct 2008 | A1 |
20080263676 | Mo et al. | Oct 2008 | A1 |
20080270730 | Lasser et al. | Oct 2008 | A1 |
20080282106 | Shalvi et al. | Nov 2008 | A1 |
20080288714 | Salomon et al. | Nov 2008 | A1 |
20090013233 | Radke | Jan 2009 | A1 |
20090024905 | Shalvi et al. | Jan 2009 | A1 |
20090034337 | Aritome | Feb 2009 | A1 |
20090043831 | Antonopoulos et al. | Feb 2009 | A1 |
20090043951 | Shalvi et al. | Feb 2009 | A1 |
20090049234 | Oh et al. | Feb 2009 | A1 |
20090073762 | Lee et al. | Mar 2009 | A1 |
20090086542 | Lee et al. | Apr 2009 | A1 |
20090089484 | Chu | Apr 2009 | A1 |
20090091979 | Shalvi | Apr 2009 | A1 |
20090094930 | Schwoerer | Apr 2009 | A1 |
20090106485 | Anholt | Apr 2009 | A1 |
20090112949 | Ergan et al. | Apr 2009 | A1 |
20090132755 | Radke | May 2009 | A1 |
20090144600 | Perlmutter et al. | Jun 2009 | A1 |
20090150894 | Huang et al. | Jun 2009 | A1 |
20090157950 | Selinger | Jun 2009 | A1 |
20090157964 | Kasorla et al. | Jun 2009 | A1 |
20090158126 | Perlmutter et al. | Jun 2009 | A1 |
20090168524 | Golov et al. | Jul 2009 | A1 |
20090172257 | Prins et al. | Jul 2009 | A1 |
20090172261 | Prins et al. | Jul 2009 | A1 |
20090193184 | Yu et al. | Jul 2009 | A1 |
20090199074 | Sommer et al. | Aug 2009 | A1 |
20090204824 | Lin et al. | Aug 2009 | A1 |
20090204872 | Yu et al. | Aug 2009 | A1 |
20090213653 | Perlmutter et al. | Aug 2009 | A1 |
20090213654 | Perlmutter et al. | Aug 2009 | A1 |
20090225595 | Kim | Sep 2009 | A1 |
20090228761 | Perlmutter et al. | Sep 2009 | A1 |
20090240872 | Perlmutter et al. | Sep 2009 | A1 |
20090265509 | Klein | Oct 2009 | A1 |
20090282308 | Gutsche et al. | Nov 2009 | A1 |
20090300227 | Nochimowski et al. | Dec 2009 | A1 |
20090323412 | Mokhlesi et al. | Dec 2009 | A1 |
20090327608 | Eschmann | Dec 2009 | A1 |
20100017650 | Chin et al. | Jan 2010 | A1 |
20100034022 | Dutta et al. | Feb 2010 | A1 |
20100057976 | Lasser | Mar 2010 | A1 |
20100061151 | Miwa et al. | Mar 2010 | A1 |
20100077279 | Kim et al. | Mar 2010 | A1 |
20100082883 | Chen et al. | Apr 2010 | A1 |
20100083247 | Kanevsky et al. | Apr 2010 | A1 |
20100110580 | Takashima | May 2010 | A1 |
20100124088 | Shalvi et al. | May 2010 | A1 |
20100131697 | Alrod et al. | May 2010 | A1 |
20100131827 | Sokolov et al. | May 2010 | A1 |
20100142268 | Aritome | Jun 2010 | A1 |
20100142277 | Yang et al. | Jun 2010 | A1 |
20100157675 | Shalvi et al. | Jun 2010 | A1 |
20100165689 | Rotbard et al. | Jul 2010 | A1 |
20100169547 | Ou | Jul 2010 | A1 |
20100169743 | Vogan et al. | Jul 2010 | A1 |
20100174847 | Paley et al. | Jul 2010 | A1 |
20100195390 | Shalvi | Aug 2010 | A1 |
20100199150 | Shalvi et al. | Aug 2010 | A1 |
20100211803 | Lablans | Aug 2010 | A1 |
20100220509 | Sokolov et al. | Sep 2010 | A1 |
20100220510 | Shalvi | Sep 2010 | A1 |
20100250836 | Sokolov et al. | Sep 2010 | A1 |
20100287217 | Borchers et al. | Nov 2010 | A1 |
20110010489 | Yeh | Jan 2011 | A1 |
20110060969 | Ramamoorthy et al. | Mar 2011 | A1 |
20110066793 | Burd | Mar 2011 | A1 |
20110075482 | Shepard et al. | Mar 2011 | A1 |
20110107049 | Kwon et al. | May 2011 | A1 |
20110149657 | Haratsch et al. | Jun 2011 | A1 |
20110199823 | Bar-Or et al. | Aug 2011 | A1 |
20110302354 | Miller | Dec 2011 | A1 |
Number | Date | Country |
---|---|---|
0783754 | Jul 1997 | EP |
1434236 | Jun 2004 | EP |
1605509 | Dec 2005 | EP |
9610256 | Apr 1996 | WO |
9828745 | Jul 1998 | WO |
2002100112 | Dec 2002 | WO |
03100791 | Dec 2003 | WO |
2007046084 | Apr 2007 | WO |
2007132452 | Nov 2007 | WO |
2007132453 | Nov 2007 | WO |
2007132456 | Nov 2007 | WO |
2007132457 | Nov 2007 | WO |
2007132458 | Nov 2007 | WO |
2007146010 | Dec 2007 | WO |
2008026203 | Mar 2008 | WO |
2008053472 | May 2008 | WO |
2008053473 | May 2008 | WO |
2008068747 | Jun 2008 | WO |
2008077284 | Jul 2008 | WO |
2008083131 | Jul 2008 | WO |
2008099958 | Aug 2008 | WO |
2008111058 | Sep 2008 | WO |
2008124760 | Oct 2008 | WO |
2008139441 | Nov 2008 | WO |
2009037691 | Mar 2009 | WO |
2009037697 | Mar 2009 | WO |
2009038961 | Mar 2009 | WO |
2009050703 | Apr 2009 | WO |
2009053961 | Apr 2009 | WO |
2009053962 | Apr 2009 | WO |
2009053963 | Apr 2009 | WO |
2009063450 | May 2009 | WO |
2009072100 | Jun 2009 | WO |
2009072101 | Jun 2009 | WO |
2009072102 | Jun 2009 | WO |
2009072103 | Jun 2009 | WO |
2009072104 | Jun 2009 | WO |
2009072105 | Jun 2009 | WO |
2009074978 | Jun 2009 | WO |
2009074979 | Jun 2009 | WO |
2009078006 | Jun 2009 | WO |
2009095902 | Aug 2009 | WO |
2011024015 | Mar 2011 | WO |
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U.S. Appl. No. 12/323,544 Office Action dated Dec. 13, 2011. |
U.S. Appl. No. 12/332,368 Office Action dated Nov. 10, 2011. |
U.S. Appl. No. 12/063,544 Office Action dated Dec. 14, 2011. |
U.S. Appl. No. 12/186,867 Office Action dated Jan. 17, 2012. |
U.S. Appl. No. 12/119,069 Office Action dated Nov. 14, 2011. |
U.S. Appl. No. 12/037,487 Office Action dated Jan. 3, 2012. |
U.S. Appl. No. 11/995,812 Office Action dated Oct. 28, 2011. |
U.S. Appl. No. 12/551,567 Office Action dated Oct. 27, 2011. |
U.S. Appl. No. 12/618,732 Office Action dated Nov. 4, 2011. |
U.S. Appl. No. 12/649,382 Office Action dated Jan. 6, 2012. |
U.S. Appl. No. 13/284,909 filed on Oct. 30, 2011. |
U.S. Appl. No. 13/284,913 filed on Oct. 30, 2011. |
U.S. Appl. No. 13/338,335 filed on Dec. 28, 2011. |
U.S. Appl. No. 13/355,536 filed on Jan. 22, 2012. |
Kim et al., “Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding”, Proceedings of the 40th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-40), Chicago, USA, Dec. 1-5, 2007. |
Hong et al., “NAND Flash-based Disk Cache Using SLC/MLC Combined Flash Memory”, 2010 International Workshop on Storage Network Architecture and Parallel I/Os, pp. 21-30, USA, May 3, 2010. |
U.S. Appl. No. 11/945,575 Official Action dated Aug. 24, 2010. |
U.S. Appl. No. 12/045,520 Official Action dated Nov. 16, 2010. |
U.S. Appl. No. 12/323,544 Official Action dated Mar. 9, 2012. |
Chinese Patent Application # 200780026181.3 Official Action dated Mar. 7, 2012. |
Chinese Patent Application # 200780026094.8 Official Action dated Feb. 2, 2012. |
U.S. Appl. No. 12/332,370 Official Action dated Mar. 8, 2012. |
U.S. Appl. No. 12/579,432 Official Action dated Feb. 29, 2012. |
U.S. Appl. No. 12/522,175 Official Action dated Mar. 27, 2012. |
U.S. Appl. No. 12/607,085 Official Action dated Mar. 28, 2012. |
Budilovsky et al., “Prototyping a High-Performance Low-Cost Solid-State Disk”, SYSTOR—The 4th Annual International Systems and Storage Conference, Haifa, Israel, May 30-Jun. 1, 2011. |
NVM Express Protocol, “NVM Express”, Revision 1.0b, Jul. 12, 2011. |
SCSI Protocol, “Information Technology—SCSI Architecture Model—5 (SAM-5)”, INCITS document T10/2104-D, revision 01, Jan. 28, 2009. |
SAS Protocol, “Information Technology—Serial Attached SCSI—2 (SAS-2)”, INCITS document T10/1760-D, revision 15a, Feb. 22, 2009. |
US 7,161,836, 01/09/2007, Wan et al. (Withdrawn). |
U.S. Appl. No. 11/995,814 Official Action dated Dec. 17, 2010. |
U.S. Appl. No. 12/388,528 Official Action dated Nov. 29, 2010. |
U.S. Appl. No. 12/251,471 Official Action dated Jan. 3, 2011. |
Engineering Windows 7, “Support and Q&A for Solid-State Drives”, e7blog, May 5, 2009. |
Micron Technology Inc., “Memory Management in NAND Flash Arrays”, Technical Note, year 2005. |
Kang et al., “A Superblock-based Flash Translation Layer for NAND Flash Memory”, Proceedings of the 6th ACM & IEEE International Conference on Embedded Software, pp. 161-170, Seoul, Korea, Oct. 22-26, 2006. |
Park et al., “Sub-Grouped Superblock Management for High-Performance Flash Storages”, IEICE Electronics Express, vol. 6, No. 6, pp. 297-303, Mar. 25, 2009. |
Ubuntu Forums, “Memory Stick Failed 10 Superblock”, posted Nov. 11, 2009. |
Super User Forums, “SD Card Failure, can't read superblock”, posted Aug. 8, 2010. |
U.S. Appl. No. 12/987,174, filed Jan. 10, 2011. |
U.S. Appl. No. 12/987,175, filed on Jan. 10, 2011. |
U.S. Appl. No. 12/963,649, filed Dec. 9, 2010. |
U.S. Appl. No. 13/021,754, filed Feb. 6, 2011. |
U.S. Appl. No. 12/534,898 Official Action dated Mar. 23, 2011. |
U.S. Appl. No. 13/047,822, filed Mar. 15, 2011. |
U.S. Appl. No. 13/069,406, filed Mar. 23, 2011. |
U.S. Appl. No. 13/088,361, filed Apr. 17, 2011. |
Ankolekar et al., “Multibit Error-Correction Methods for Latency-Constrained Flash Memory Systems”, IEEE Transactions on Device and Materials Reliability, vol. 10, No. 1, pp. 33-39, Mar. 2010. |
U.S. Appl. No. 12/344,233 Official Action dated Jun. 24, 2011. |
U.S. Appl. No. 11/995,813 Official Action dated Jun. 16, 2011. |
Berman et al., “Mitigating Inter-Cell Coupling Effects in MLC NAND Flash via Constrained Coding”, Flash Memory Summit, Santa Clara, USA, Aug. 19, 2010. |
U.S. Appl. No. 12/178,318 Official Action dated May 31, 2011. |
CN Patent Application # 200780026181.3 Official Action dated Apr. 8, 2011. |
Agrell et al., “Closest Point Search in Lattices”, IEEE Transactions on Information Theory, vol. 48, No. 8, pp. 2201-2214, Aug. 2002. |
Bez et al., “Introduction to Flash memory”, Proceedings of the IEEE, vol. 91, No. 4, pp. 489-502, Apr. 2003. |
Blahut, R.E., “Theory and Practice of Error Control Codes,” Addison-Wesley, May, 1984, section 3.2, pp. 47-48. |
Chang, L., “Hybrid Solid State Disks: Combining Heterogeneous NAND Flash in Large SSDs”, ASPDAC, Jan. 2008. |
Cho et al., “Multi-Level NAND Flash Memory with Non-Uniform Threshold Voltage Distribution,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 5-7, 2001, pp. 28-29 and 424. |
Databahn™, “Flash memory controller IP”, Denali Software, Inc., 1994 https://www.denali.com/en/products/databahn—flash.jsp. |
Datalight, Inc., “FlashFX Pro 3.1 High Performance Flash Manager for Rapid Development of Reliable Products”, Nov. 16, 2006. |
Duann, N., Silicon Motion Presentation “SLC & MLC Hybrid”, Flash Memory Summit, Santa Clara, USA, Aug. 2008. |
Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), pp. 522-524, Tokyo, Japan 1999. |
Eitan et al., “Multilevel Flash Cells and their Trade-Offs”, Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), pp. 169-172, New York, USA 1996. |
Engh et al., “A self adaptive programming method with 5 mV accuracy for multi-level storage in Flash”, pp. 115-118, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, May 12-15, 2002. |
Goodman et al., “On-Chip ECC for Multi-Level Random Access Memories,” Proceedings of the IEEE/CAM Information Theory Workshop, Ithaca, USA, Jun. 25-29, 1989. |
Han et al., “An Intelligent Garbage Collection Algorithm for Flash Memory Storages”, Computational Science and Its Applications—ICCSA 2006, vol. 3980/2006, pp. 1019-1027, Springer Berlin / Heidelberg, Germany, May 11, 2006. |
Han et al., “CATA: A Garbage Collection Scheme for Flash Memory File Systems”, Ubiquitous Intelligence and Computing, vol. 4159/2006, pp. 103-112, Springer Berlin / Heidelberg, Aug. 25, 2006. |
Horstein, “On the Design of Signals for Sequential and Nonsequential Detection Systems with Feedback,” IEEE Transactions on Information Theory IT-12:4 (Oct. 1966), pp. 448-455. |
Jung et al., in “A 117 mm.sup.2 3.3V Only 128 Mb Multilevel NAND Flash Memory for Mass Storage Applications,” IEEE Journal of Solid State Circuits, (11:31), Nov. 1996, pp. 1575-1583. |
Kawaguchi et al. 1995. A flash-memory based file system. In Proceedings of the USENIX 1995 Technical Conference , New Orleans, Louisiana. 155-164. |
Kim et al., “Future Memory Technology including Emerging New Memories”, Proceedings of the 24th International Conference on Microelectronics (MIEL), vol. 1, pp. 377-384, Nis, Serbia and Montenegro, May 16-19, 2004. |
Lee et al., “Effects of Floating Gate Interference on NAND Flash Memory Cell Operation”, IEEE Electron Device Letters, vol. 23, No. 5, pp. 264-266, May 2002. |
Maayan et al., “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State circuits Conference (ISSCC 2002), pp. 100-101, San Francisco, USA, Feb. 3-7, 2002. |
Mielke et al., “Recovery Effects in the Distributed Cycling of Flash Memories”, IEEE 44th Annual International Reliability Physics Symposium, pp. 29-35, San Jose, USA, Mar. 2006. |
Onfi, “Open NAND Flash Interface Specification,” revision 1.0, Dec. 28, 2006. |
Phison Electronics Corporation, “PS8000 Controller Specification (for SD Card)”, revision 1.2, Document No. S-07018, Mar. 28, 2007. |
Shalvi, et al., “Signal Codes,” Proceedings of the 2003 IEEE Information Theory Workshop (ITW'2003), Paris, France, Mar. 31-Apr. 4, 2003. |
Shiozaki, A., “Adaptive Type-II Hybrid Broadcast ARQ System”, IEEE Transactions on Communications, vol. 44, Issue 4, pp. 420-422, Apr. 1996. |
Suh et al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, pp. 1149-1156, Nov. 1995. |
ST Microelectronics, “Bad Block Management in NAND Flash Memories”, Application note AN-1819, Geneva, Switzerland, May 2004. |
ST Microelectronics, “Wear Leveling in Single Level Cell NAND Flash Memories,” Application note AN-1822 Geneva, Switzerland, Feb. 2007. |
Takeuchi et al., “A Double Level VTH Select Gate Array Architecture for Multi-Level NAND Flash Memories”, Digest of Technical Papers, 1995 Symposium on VLSI Circuits, pp. 69-70, Jun. 8-10, 1995. |
Takeuchi et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories”, IEEE Journal of Solid State Circuits, vol. 33, No. 8, Aug. 1998. |
Wu et al., “eNVy: A non-Volatile, Main Memory Storage System”, Proceedings of the 6th International Conference on Architectural support for programming languages and operating systems, pp. 86-87, San Jose, USA, 1994. |
Sommer, N., U.S. Appl. No. 12/171,797 “Memory Device with Non-Uniform Programming Levels” filed Jul. 11, 2008. |
Shalvi et al., U.S. Appl. No. 12/251,471 “Compensation for Voltage Drifts in Analog Memory Cells” filed Oct. 15, 2008. |
Sommer et al., U.S. Appl. No. 12/497,707 “Data Storage in Analog Memory Cells with Protection Against Programming Interruption” filed Jul. 6, 2009. |
Winter et al., U.S. Appl. No. 12/534,893 “Improved Data Storage in Analog Memory Cells Using Modified Pass Voltages” filed Aug. 4, 2009. |
Winter et al., U.S. Appl. No. 12/534,898 “Data Storage Using Modified Voltages” filed Aug. 4, 2009. |
Shalvi et al., U.S. Appl. No. 12/551,583 “Segmented Data Storage” filed Sep. 1, 2009. |
Shalvi et al., U.S. Appl. No. 12/551,567 “Reliable Data Storage in Analog Memory Cells Subjected to Long Retention Periods” filed Sep. 1, 2009. |
Perlmutter et al., U.S. Appl. No. 12/558,528 “Estimation of Memory Cell Read Thresholds by Sampling Inside Programming Level Distribution Intervals” filed Sep. 13, 2009. |
Sokolov, D., U.S. Appl. No. 12/579,430 “Efficient Programming of Analog Memory Cell Devices” filed Oct. 15, 2009. |
Shalvi, O., U.S. Appl. No. 12/579,432 “Efficient Data Storage in Storage Device Arrays” filed Oct. 15, 2009. |
Sommer et al., U.S. Appl. No. 12/607,078 “Data Scrambling in Memory Devices” filed Oct. 28, 2009. |
Sommer et al., U.S. Appl. No. 12/607,085 “Data Scrambling Schemes for Memory Devices” filed Oct. 28, 2009. |
Sommer et al., U.S. Appl. No. 12/649,358 “Efficient Readout Schemes for Analog Memory Cell Devices” filed Dec. 30, 2009. |
Sommer et al., U.S. Appl. No. 12/649,360 “Efficient Readout Schemes for Analog Memory Cell Devices Using Multiple Read Threshold Sets” filed Dec. 30, 2009. |
Shachar et al. U.S. Appl. No. 12/688,883 “Hierarchical data storage system” filed Jan. 17, 2010. |
Sommer et al., U.S. Appl. No. 12/728,296 “Database of Memory Read Thresholds” filed Mar. 22, 2010. |
Sommer et al., U.S. Appl. No. 12/758,003 “Selective re-programming of analog memory cells” filed Apr. 11, 2010. |
Huffman, A., “Non-Volatile Memory Host Controller Interface (NVMHCI)”, Specification 1.0, Apr. 14, 2008. |
U.S. App. No. 11/957,970 Official Action dated May 20, 2010. |
Panchbhai et al., “Improving Reliability of NAND Based Flash Memory Using Hybrid SLC/MLC Device”, Project Proposal for CSci 8980—Advanced Storage Systems, University of Minnesota, USA, Spring 2009. |
Jedec Standard JESD84-C44, “Embedded MultiMediaCard (eMMC) Mechanical Standard, with Optional Reset Signal”, Jedec Solid State Technology Association, USA, Jul. 2009. |
Jedec, “UFS Specification”, version 0.1, Nov. 11, 2009. |
SD Group and SD Card Association, “SD Specifications Part 1 Physical Layer Specification”, version 3.01, draft 1.00, Nov. 9, 2009. |
Compaq et al., “Universal Serial Bus Specification”, revision 2.0, Apr. 27, 2000. |
Serial ATA International Organization, “Serial ATA Revision 3.0 Specification”, Jun. 2, 2009. |
Gotou, H., “An Experimental Confirmation of Automatic Threshold Voltage Convergence in a Flash Memory Using Alternating Word-Line Voltage Pulses”, IEEE Electron Device Letters, vol. 18, No. 10, pp. 503-505, Oct. 1997. |
U.S. Appl. No. 12/880,101 “Reuse of Host Hibernation Storage Space by Memory Controller”, filed Sep. 12, 2010. |
U.S. Appl. No. 12/890,724 “Error Coding Over Multiple Memory pp.”, filed Sep. 27, 2010. |
U.S. Appl. No. 12/171,797 Official Action dated Aug. 25, 2010. |
U.S. Appl. No. 12/497,707 Official Action dated Sep. 15, 2010. |
U.S. Appl. No. 11/995,801 Official Action dated Oct. 15, 2010. |
Numonyx, “M25PE16: 16-Mbit, page-erasable serial flash memory with byte-alterability, 75 MHz SPI bus, standard pinout”, Apr. 8. |
Shalvi et al., U.S. Appl. No. 12/822,207 “Adaptive Over-Provisioning in Memory Systems” filed Jun. 24, 2010. |
Wei, L., “Trellis-Coded Modulation With Multidimensional Constellations”, IEEE Transactions on Information Theory, vol. IT-33, No. 4, pp. 483-501, Jul. 1987. |
U.S. Appl. No. 13/114,049 Official Action dated Sep. 12, 2011. |
U.S. Appl. No. 12/405,275 Official Action dated Jul. 29, 2011. |
Chinese Patent Application # 200780040493.X Official Action dated Jun. 15, 2011. |
U.S. Appl. No. 12/037,487 Official Action dated Oct. 3, 2011. |
U.S. Appl. No. 12/649,360 Official Action dated Aug. 9, 2011. |
U.S. Appl. No. 13/192,504, filed Jul. 28, 2011. |
U.S. Appl. No. 13/192,852, filed Aug. 2, 2011. |
U.S. Appl. No. 13/231,963, filed Sep. 14, 2011. |
U.S. Appl. No. 13/239,408, filed Sep. 22, 2011. |
U.S. Appl. No. 13/239,411, filed Sep. 22, 2011. |
U.S. Appl. No. 13/214,257, filed Aug. 22, 2011. |
U.S. Appl. No. 13/192,501, filed Jul. 28, 2011. |
U.S. Appl. No. 13/192,495, filed Jul. 28, 2011. |
Number | Date | Country | |
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61251807 | Oct 2009 | US |