Patent Application
20080163013
Random-access memory (RAM) technology has matured to the extent that present device topologies are several times the data width of early memory devices. Memories that are two hundred fifty-six and five hundred twelve bits wide are now routinely manufactured. RAM topologies that are wider still can probably be expected in the foreseeable future.
It is common practice to test such RAM devices in significant numbers, be they commercially deliverable lots, statistically viable populations of a new RAM design, etc. Such testing typically involves writing and reading known data (i.e., vectors) to and from each tested device while detecting any discrepancies that occur. The cost and complexity of such memory testing systems are of growing concern. As RAM devices have become wider (i.e., more bits per line), the number of required connection points, signal traces and wires, and discrete components in the test assembly have increased correspondingly. State-of-the-art RAM topologies are such that considerable complexity and cost is involved in constructing and operating the required test equipment.
Numerous testing methods are used to combat cost and/or complexity issues as exemplified above. One such method is known as “data slicing”. While this approach substantially simplifies the required test apparatus, it has the undesirable effect of greatly increasing the apparent depth of the RAM device under test. In turn, this apparent increase in depth increases the number of test cycles and overall time required to test a particular RAM device.
One known memory testing topology 20 is depicted in
The topology 20 of
After the RAM device 22 has been written to (fully or partially), the test data is then progressively read from the RAM device 22, one double-word (i.e., line) at a time. This data is received from the RAM device 22 by way of four respective eight-bit signal pathways 34. These four pathways 34 collectively define thirty-two bit-signals 36. The four bit-signal pathways 34 are also routed to a multiplexer 38. The multiplexer 38 is configured to take two bit-signals from each of the pathways 34 and combine them into a test output byte 40. In this way, each test output byte 40 is derived from a double-word that was previously stored in the RAM device 22. Each test output 40 byte can then be evaluated by other circuitry or means (not shown) to determine if there are discrepancies between a portion of the test data loaded into the RAM device 22, and that portion which is read from the RAM device 22.
Because each test output byte 40 represents only one-fourth of the total width of the RAM device 22, four iterations are required to fully test the overall storage capacity of the RAM device 22. This time expenditure trade-off has been tolerated in the past in order to simplify the overall testing apparatus. However, a solution that avoids both excessive testing time and increased test apparatus complexity is desired.
In one embodiment, logic circuitry is coupled to all of the data outputs of a RAM device under test. Such data outputs are discretely referred to as bit signals. As test vectors are read from the RAM device, the logic circuitry determines if all of the bit-signals within selected sub-pluralities of the bit-signals are of the same (equal) logical value. An output signal is provided indicating if such equality has been determined for all of the sub-pluralities, on a line-by-line basis. This output signal can then be used alone or in conjunction with other testing techniques to evaluate the storage and read integrity of the RAM device under test.
Overview of Testing System
The system 100 also includes a multiplexer (MUX) 106 that receives all of the signal pathways 104. The multiplexer 106 is configured to take (or select) two predetermined bit-signals from each incoming bit-signal pathway 104 and combine them into an output 108 that is eight bit-signals in width. Under typical operation of the system 100, the multiplexer 106 produces one output 108 byte for each double-word (thirty-two bits) of data that is read from the RAM device 102 under test. Each of these output 108 bytes can be sent on to other testing and evaluation circuitry (not shown) as desired.
The system 100 further includes logic circuitry 110. The logic circuitry 110, as will be described in detail below, can be provided in any suitable manner including, but not limited to: a circuit comprising one or more discrete logic devices; an application specific integrated circuit (ASIC); a programmable logic device; etc. Other suitable means can also be used to define and provide the logic circuitry 110, or selected portions thereof.
The logic circuitry 110 of
Each sub-circuit 112 of
The logic circuitry 110 of the system 100 includes an AND logic gate 120. The AND logic gate 120 is configured to receive all of the signals 118 and provide an output signal 122 asserted to indicate equality if, and only if, all of the sub-circuits 112 indicated equality for the bit-signals respectively tested by each. In this way, the output signal 122 provides a go/no-go type indication with respect to all of the bit-signals read from the RAM device 102. Thus, the output signal 122 provides a single test point that can be used alone or in conjunction with the output byte 108 in while the RAM device 102 is under test.
During typical testing operations of the system 100 of
Then, as the test vectors (i.e., data) are read, or “clocked out”, of the RAM device 102, the logic circuitry 110 is able to provide a single test-point output signal 122 indicating if even a single bit discrepancy (or more) is present within a particular double-word read form the RAM device 102. Because the RAM device 102 is understood to be address-accessible, the particular storage line within the RAM device 102 where a data discrepancy has occurred is readily determinable.
The sub-circuit 112 includes an AND logic gate 130 and a NOR logic gate 132. Each of the AND and NOR logic gates 130, 132 is configured to receive four bit-signals collectively referred to as bit-signals 136. Each of the bit-signals 136 is coupled to a respect one of the bit-signals within each of the signal pathways 104 of
In turn, the AND logic gate 130 and the NOR logic gate 132 produce respective signals 138 and 140 in accordance with the logical evaluation that each performs on the incoming bit-signals 136. One of ordinary skill in the electrical engineering and related arts can appreciate the respective logical operations performed by the AND and NOR logic gates 130, 132. Such operations are further described hereinafter.
The sub-circuit 112 of
The Table 1 above reveals the respective internal and overall operations of the sub-circuit 112 of
Specifically, the AND logic gate 130 provides a signal 138 that is asserted “one” only when all of the bit-signals 136 are asserted “one” (i.e., input state “P”). In comparison, the NOR logic gate 132 provides a signal 140 that is asserted “one” only when all of the bit-signals 136 are asserted “zero” (i.e., input state “A”). In turn, the XOR logic gate 134 provides an output signal 118 that is asserted “one” only when one or the other (but not both) of signals 138 or 140 is asserted “one” (i.e., input states “A” and “P” only). Under all other input states “B” through “O”, the XOR gate provides a signal 118 that is asserted “zero”. The output signal 118 routed to the AND logic gate 120 of the logic circuitry 110 of the system 100 of
Exemplary Method
At step 202, one or more known test vectors are written into a RAM device to be tested. Such test vectors typically include one or more sub-pluralities of bits, wherein all bits are set to “one” or all “zero” within a particular sub-plurality. In any case, sufficient test vectors are written to the RAM device to fill all of the device, or to a selected address or addresses, within the RAM device. In this way, all or selected portions of the RAM device can be subjected to storage and retrieval (i.e., write and read) integrity testing.
At step 204, data is read from the RAM device, one line at a time in address-selective succession. Thus, plural bit-signals are read from the RAM device in count-dependence upon the width of line storage (e.g., thirty-two, sixty-four, etc.) of the particular RAM under test.
At step 206, the plural bit signals are segregated into sub-pluralities, or groupings, of bit-signals. In one exemplary embodiment, a RAM device being thirty-two bits wide has its bit-signals segregated into eight sub-pluralities of four bit-signals each. Other segregation schemes corresponding to other embodiments can also be used.
At step 208, each of the sub-pluralities of bit signals is independently tested to determine if all bit-signals (e.g. four, etc.) therein are of equal logical value. An output signal indicating equality or non-equality is provided or generated for each of the sub-pluralities.
At step 210, the equality/non-equality determinations made for each of the sub-pluralities are collectively evaluated. If all sub-pluralities indicated equality, then an overall output signal is asserted accordingly and provided. Otherwise, if even a single sub-plurality indicates non-equality, then the overall output signal is asserted to indicate non-equality.
The various embodiments described above can substantially expedite testing of RAM devices and other memory device types. The logic circuitry provided herein can be suitably adapted numerous storage topologies such as, for example, 8 k lines by 32 bits wide, 4 k line by 64 bits wide, etc. Overall system complexity is reduced and the total line-by-line storage capacity of a RAM device can be evaluated during a single pass of testing.
Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claimed invention.
