Methods of manufacturing layer connectors involving a specific sequence of method steps

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H01L2224/279

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/279Methods of manufacturing layer connectors involving a specific sequence of method steps

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Patents Grantslast 30 patents

Information Patent Grant
Anisotropic conductive film with carbon-based conductive regions an...
- Patent number 11,881,468
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Eiichi Nakano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric and metallic nanowire bond layers
- Patent number 11,791,296
- Issue date Oct 17, 2023
- Texas Instruments Incorporated
- Scott Robert Summerfelt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of measuring underfill profile of underfill cavity having so...
- Patent number 11,355,361
- Issue date Jun 7, 2022
- Coretech System Co., Ltd.
- Yu-En Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric and metallic nanowire bond layers
- Patent number 11,195,811
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Scott Robert Summerfelt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anisotropic conductive film with carbon-based conductive regions an...
- Patent number 11,189,588
- Issue date Nov 30, 2021
- Micron Technology, Inc.
- Eiichi Nakano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing perovskite solar cell module and perovskit...
- Patent number 11,114,252
- Issue date Sep 7, 2021
- CPC CORPORATION, TAIWAN
- Kuan-Chieh Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,770,333
- Issue date Sep 8, 2020
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,770,332
- Issue date Sep 8, 2020
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ag underlayer-attached metallic member, Ag underlayer-attached insu...
- Patent number 10,734,297
- Issue date Aug 4, 2020
- Mitsubishi Materials Corporation
- Shuji Nishimoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,707,111
- Issue date Jul 7, 2020
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anisotropic conductive film (ACF) and forming method thereof, ACF r...
- Patent number 10,510,708
- Issue date Dec 17, 2019
- BOE Technology Group Co., Ltd.
- Wei Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hermetically sealed MEMS device and its fabrication
- Patent number 10,427,932
- Issue date Oct 1, 2019
- Texas Instruments Incorporated
- John Charles Ehmke
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
3D packaging method for semiconductor components
- Patent number 10,418,339
- Issue date Sep 17, 2019
- Imec VZW
- Fabrice Duval
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 10,269,609
- Issue date Apr 23, 2019
- Semiconductor Components Industries, LLC
- Darrell D. Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding method for connecting two wafers
- Patent number 10,134,707
- Issue date Nov 20, 2018
- Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung E.V.
- Kai Zoschke
- B32 - LAYERED PRODUCTS
Information Patent Grant
Wafer level flat no-lead semiconductor packages and methods of manu...
- Patent number 9,892,952
- Issue date Feb 13, 2018
- Semiconductor Components Industries, LLC
- Darrell Truhitte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device mounting method
- Patent number 9,793,221
- Issue date Oct 17, 2017
- Fujitsu Limited
- Hidehiko Kira
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer to wafer bonding process and structures
- Patent number 9,613,926
- Issue date Apr 4, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Embedded electrical component surface interconnect
- Patent number 9,245,819
- Issue date Jan 26, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Michael B. Vincent
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
3D integrated heterostructures having low-temperature bonded interf...
- Patent number 9,117,686
- Issue date Aug 25, 2015
- Soitec
- Gweltaz Gaudin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Low-temperature bonding process
- Patent number 8,790,992
- Issue date Jul 29, 2014
- Soitec
- Gweltaz Gaudin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Part mounting method
- Patent number 8,769,810
- Issue date Jul 8, 2014
- Fujitsu Limited
- Toru Nishino
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of manufacturing semiconductor device, manufacturing program...
- Patent number 8,691,628
- Issue date Apr 8, 2014
- Kabushiki Kaisha Toshiba
- Yasuo Tane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing semiconductor device
- Patent number 8,629,041
- Issue date Jan 14, 2014
- Kabushiki Kaisha Toshiba
- Yasuo Tane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing semiconductor device and semiconductor man...
- Patent number 8,276,537
- Issue date Oct 2, 2012
- Kabushiki Kaisha Toshiba
- Yukio Katamura
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for mounting electronic components
- Patent number 8,230,590
- Issue date Jul 31, 2012
- Fujitsu Semiconductor Limited
- Takao Nishimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Flip chip underfill process
- Patent number 6,861,285
- Issue date Mar 1, 2005
- Intel Corporation
- Rajen C. Dias
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip device with multi-layered underfill having graded coeffic...
- Patent number 6,815,831
- Issue date Nov 9, 2004
- Intel Corporation
- Rajen C. Dias
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Manufacturing method of a system in package having several layers a...
- Publication number 20250038121
- Publication date Jan 30, 2025
- THALES
- Damien CHALAVOUX
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SENSOR PACKAGE
- Publication number 20240304639
- Publication date Sep 12, 2024
- SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Yu-Te Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AN...
- Publication number 20240170435
- Publication date May 23, 2024
- Micron Technology, Inc.
- Eiichi Nakano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS
- Publication number 20220102307
- Publication date Mar 31, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Scott Robert SUMMERFELT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMALLY CONDUCTIVE SHEET, METHOD FOR MANUFACTURING THE SAME, AND...
- Publication number 20220098462
- Publication date Mar 31, 2022
- DEXERIALS CORPORATION
- Marina TOBATA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AN...
- Publication number 20220077098
- Publication date Mar 10, 2022
- Micron Technology, Inc.
- Eiichi Nakano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS
- Publication number 20200321304
- Publication date Oct 8, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Scott Robert SUMMERFELT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AN...
- Publication number 20200211996
- Publication date Jul 2, 2020
- Micron Technology, Inc.
- Eiichi Nakano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANISOTROPIC CONDUCTIVE FILM (ACF) AND FORMING METHOD THEREOF, ACF R...
- Publication number 20190035760
- Publication date Jan 31, 2019
- BOE TECHNOLOGY GROUP CO., LTD.
- Wei LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING METHOD FOR PACKAGE DEVICE
- Publication number 20180204818
- Publication date Jul 19, 2018
- Disco Corporation
- Kazuma Sekiya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...
- Publication number 20180174881
- Publication date Jun 21, 2018
- Semiconductor Components Industries, LLC
- Darrell D. TRUHITTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTEGRATED HETEROSTRUCTURES HAVING LOW-TEMPERATURE BONDED INTERF...
- Publication number 20140327113
- Publication date Nov 6, 2014
- Gweltaz Gaudin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Embedded Electrical Component Surface Interconnect
- Publication number 20130215583
- Publication date Aug 22, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Michael B. Vincent
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MAN...
- Publication number 20120318431
- Publication date Dec 20, 2012
- Kabushiki Kaisha Toshiba
- Yukio KATAMURA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MANUFACTURING PROGRAM...
- Publication number 20120149151
- Publication date Jun 14, 2012
- Kabushiki Kaisha Toshiba
- Yasuo TANE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-TEMPERATURE BONDING PROCESS
- Publication number 20120043647
- Publication date Feb 23, 2012
- Gweltaz M. Gaudin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number 20110263078
- Publication date Oct 27, 2011
- Kyocera Chemical Corporation
- Yasuo TANE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MAN...
- Publication number 20110263131
- Publication date Oct 27, 2011
- Kabushiki Kaisha Toshiba
- Yukio KATAMURA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PART MOUNTING APPARATUS AND METHOD
- Publication number 20100132187
- Publication date Jun 3, 2010
- Fujitsu Limited
- Toru Nishino
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
FLIP CHIP WAFER, FLIP CHIP DIE AND MANUFACTURING PROCESSES THEREOF
- Publication number 20090127718
- Publication date May 21, 2009
- Singjang CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MOUNTING ELECTRONIC COMPONENTS
- Publication number 20080196245
- Publication date Aug 21, 2008
- Fujitsu Limited
- Takao Nishimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Flip chip underfill process
- Publication number 20030203536
- Publication date Oct 30, 2003
- Rajen C. Dias
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip chip underfill process
- Publication number 20030109080
- Publication date Jun 12, 2003
- Rajen C. Dias
- H01 - BASIC ELECTRIC ELEMENTS

Methods of manufacturing layer connectors involving a specific sequence of method steps

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Anisotropic conductive film with carbon-based conductive regions an...

Dielectric and metallic nanowire bond layers

Method of measuring underfill profile of underfill cavity having so...

Dielectric and metallic nanowire bond layers

Anisotropic conductive film with carbon-based conductive regions an...

Method for manufacturing perovskite solar cell module and perovskit...

Wafer level flat no-lead semiconductor packages and methods of manu...

Wafer level flat no-lead semiconductor packages and methods of manu...

Ag underlayer-attached metallic member, Ag underlayer-attached insu...

Wafer level flat no-lead semiconductor packages and methods of manu...

Anisotropic conductive film (ACF) and forming method thereof, ACF r...

Hermetically sealed MEMS device and its fabrication

3D packaging method for semiconductor components

Wafer level flat no-lead semiconductor packages and methods of manu...

Bonding method for connecting two wafers

Wafer level flat no-lead semiconductor packages and methods of manu...

Semiconductor device mounting method

Wafer to wafer bonding process and structures

Embedded electrical component surface interconnect

3D integrated heterostructures having low-temperature bonded interf...

Low-temperature bonding process

Part mounting method

Method of manufacturing semiconductor device, manufacturing program...

Method for manufacturing semiconductor device

Method for manufacturing semiconductor device and semiconductor man...

Method for mounting electronic components

Flip chip underfill process

Flip-chip device with multi-layered underfill having graded coeffic...

Patents Applicationslast 30 patents

Manufacturing method of a system in package having several layers a...

OPTICAL SENSOR PACKAGE

ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AN...

DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS

THERMALLY CONDUCTIVE SHEET, METHOD FOR MANUFACTURING THE SAME, AND...

ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AN...

DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS

ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AN...

ANISOTROPIC CONDUCTIVE FILM (ACF) AND FORMING METHOD THEREOF, ACF R...

MANUFACTURING METHOD FOR PACKAGE DEVICE

WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANU...

3D INTEGRATED HETEROSTRUCTURES HAVING LOW-TEMPERATURE BONDED INTERF...

Embedded Electrical Component Surface Interconnect

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MAN...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MANUFACTURING PROGRAM...

LOW-TEMPERATURE BONDING PROCESS

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MAN...

PART MOUNTING APPARATUS AND METHOD

FLIP CHIP WAFER, FLIP CHIP DIE AND MANUFACTURING PROCESSES THEREOF

METHOD FOR MOUNTING ELECTRONIC COMPONENTS

Flip chip underfill process

Flip chip underfill process