Multiple simultaneous testing of subparts

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CPC
G01R31/318563

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318563Multiple simultaneous testing of subparts

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core and interface scan testing architecture and methodology
- Patent number 11,879,942
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Banadappa Shivaray
- G01 - MEASURING TESTING
Information Patent Grant
Device testing architecture, method, and system
- Patent number 11,846,673
- Issue date Dec 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device testing architecture of an integrated circuit
- Patent number 11,609,269
- Issue date Mar 21, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Utilizing single cycle ATPG test patterns to detect multicycle cell...
- Patent number 11,579,194
- Issue date Feb 14, 2023
- Cadence Design Systems, Inc.
- Arvind Chokhani
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test method and test system
- Patent number 11,320,484
- Issue date May 3, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Shu-Liang Ning
- G01 - MEASURING TESTING
Information Patent Grant
Chip testing circuit and testing method thereof
- Patent number 11,287,466
- Issue date Mar 29, 2022
- ONE TEST SYSTEMS
- Chen-Lung Tsai
- G01 - MEASURING TESTING
Information Patent Grant
Chip and testing method thereof
- Patent number 11,287,472
- Issue date Mar 29, 2022
- Realtek Semiconductor Corporation
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,243,253
- Issue date Feb 8, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microchip having a plurality of reconfigurable test structures
- Patent number 11,237,211
- Issue date Feb 1, 2022
- Hochschule Hamm-Lippstadt
- Rene Krenz-Baath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test access mechanism controller including instruction register, in...
- Patent number 11,125,818
- Issue date Sep 21, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan based test design in serdes applications
- Patent number 11,112,459
- Issue date Sep 7, 2021
- Credo Technology Group Ltd.
- Haoli Qian
- G01 - MEASURING TESTING
Information Patent Grant
Chain testing and diagnosis using two-dimensional scan architecture
- Patent number 11,092,645
- Issue date Aug 17, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Wu-Tung Cheng
- G01 - MEASURING TESTING
Information Patent Grant
Combinatorial serial and parallel test access port selection in a J...
- Patent number 11,041,905
- Issue date Jun 22, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rapid scan testing of integrated circuit chips
- Patent number 10,921,372
- Issue date Feb 16, 2021
- Seagate Technology LLC
- Rajesh Maruti Bhagwat
- G01 - MEASURING TESTING
Information Patent Grant
Channel circuitry, tap linking module, scan tap, debug tap domains
- Patent number 10,901,033
- Issue date Jan 26, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing monolithic three dimensional integrated circuits
- Patent number 10,775,429
- Issue date Sep 15, 2020
- Marvell Asia Pte., Ltd.
- Sukeshwar Kannan
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain operations
- Patent number 10,712,389
- Issue date Jul 14, 2020
- Micron Technology, Inc.
- Joshua E. Alzheimer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC taps with control register and scan router coupling taps
- Patent number 10,605,865
- Issue date Mar 31, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit supporting logic self test pattern injection dur...
- Patent number 10,598,728
- Issue date Mar 24, 2020
- STMicroelectronics (Grenoble 2) SAS
- Bruno Fel
- G01 - MEASURING TESTING
Information Patent Grant
Wafer with dio bidirectional lead, n dies, domains, clock leads
- Patent number 10,551,438
- Issue date Feb 4, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test application time reduction using capture-per-cycle test points
- Patent number 10,509,072
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor apparatus and design apparatus
- Patent number 10,496,771
- Issue date Dec 3, 2019
- Renesas Electronics Corporation
- Hiroyuki Iwata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combinatorial serial and parallel test access port selection in a J...
- Patent number 10,495,690
- Issue date Dec 3, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic circuit having serial latch scan chains
- Patent number 10,459,031
- Issue date Oct 29, 2019
- GLOBALFOUNDRIES Inc.
- Tilman Gloekler
- G01 - MEASURING TESTING
Information Patent Grant
Broadcast scan network
- Patent number 10,436,840
- Issue date Oct 8, 2019
- NVIDIA Corp.
- Jau Wu
- G01 - MEASURING TESTING
Information Patent Grant
Test method and test apparatus for testing a plurality of blocks in...
- Patent number 10,345,375
- Issue date Jul 9, 2019
- International Business Machines Corporation
- Fei Dong
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device, electronic device, and self-diagnosis method...
- Patent number 10,317,466
- Issue date Jun 11, 2019
- Renesas Electronics Corporation
- Takuro Nishikawa
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
X-Masking for In-System Deterministic Test
- Publication number 20240337693
- Publication date Oct 10, 2024
- Siemens Industry Software Inc.
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
- Publication number 20210382107
- Publication date Dec 9, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
FLEXIBLE INTERFACE
- Publication number 20210374023
- Publication date Dec 2, 2021
- STMicroelectronics (Research and Development) Limited
- Leonardo NAPOLITANO
- G01 - MEASURING TESTING
Information Patent Application
CHIP TESTING CIRCUIT AND TESTING METHOD THEREOF
- Publication number 20210311109
- Publication date Oct 7, 2021
- ONE TEST SYSTEMS
- CHEN-LUNG TSAI
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20210088584
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microchip Having A Plurality Of Reconfigurable Test Structures
- Publication number 20200271723
- Publication date Aug 27, 2020
- HOCHSCHULE HAMM-LIPPSTADT
- Rene KRENZ-BAATH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
- Publication number 20200182931
- Publication date Jun 11, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20200124667
- Publication date Apr 23, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...
- Publication number 20200064405
- Publication date Feb 27, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAPID SCAN TESTING OF INTEGRATED CIRCUIT CHIPS
- Publication number 20190339326
- Publication date Nov 7, 2019
- SEAGATE TECHNOLOGY LLC
- Rajesh Maruti Bhagwat
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20190120899
- Publication date Apr 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN OPERATIONS
- Publication number 20190120902
- Publication date Apr 25, 2019
- Micron Technology, Inc.
- Joshua E. Alzheimer
- G01 - MEASURING TESTING
Information Patent Application
DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
- Publication number 20190064263
- Publication date Feb 28, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...
- Publication number 20190064270
- Publication date Feb 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20180321307
- Publication date Nov 8, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN BASED TEST DESIGN IN SERDES APPLICATIONS
- Publication number 20180306862
- Publication date Oct 25, 2018
- CREDO TECHNOLOGY GROUP LIMITED
- Haoli Qian
- G01 - MEASURING TESTING
Information Patent Application
DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
- Publication number 20180292455
- Publication date Oct 11, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMIC CONTROLLER BIST
- Publication number 20180259578
- Publication date Sep 13, 2018
- QUALCOMM Incorporated
- Praveen Raghuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20180156867
- Publication date Jun 7, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20180128875
- Publication date May 10, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED ELECTRONIC DEVICE HAVING A TEST ARCHITECTURE, AND TEST M...
- Publication number 20180067163
- Publication date Mar 8, 2018
- STMicroelectronics S.r.l.
- Alberto Pagani
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING SYSTEM, METHOD AND APPARATUS
- Publication number 20180052202
- Publication date Feb 22, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD...
- Publication number 20180003771
- Publication date Jan 4, 2018
- Renesas Electronics Corporation
- Takuro NISHIKAWA
- G01 - MEASURING TESTING
Information Patent Application
DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
- Publication number 20170234928
- Publication date Aug 17, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Test Generation For Test-Per-Clock
- Publication number 20140372824
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology
- Publication number 20140372819
- Publication date Dec 18, 2014
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CORE CIRCUIT TEST ARCHITECTURE
- Publication number 20140359388
- Publication date Dec 4, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
System and method for optimized board test and configuration
- Publication number 20140298125
- Publication date Oct 2, 2014
- Testonica Lab OU
- Sergei DEVADZE
- G01 - MEASURING TESTING

Multiple simultaneous testing of subparts

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Systems and methods for scan chain stitching

Core and interface scan testing architecture and methodology

Device testing architecture, method, and system

Wafer scale testing using a 2 signal JTAG interface

Device testing architecture of an integrated circuit

Utilizing single cycle ATPG test patterns to detect multicycle cell...

Wafer scale testing using a 2 signal JTAG interface

Test method and test system

Chip testing circuit and testing method thereof

Chip and testing method thereof

Wafer scale testing using a 2 signal JTAG interface

Microchip having a plurality of reconfigurable test structures

Test access mechanism controller including instruction register, in...

Scan based test design in serdes applications

Chain testing and diagnosis using two-dimensional scan architecture

Combinatorial serial and parallel test access port selection in a J...

Rapid scan testing of integrated circuit chips

Channel circuitry, tap linking module, scan tap, debug tap domains

Testing monolithic three dimensional integrated circuits

Scan chain operations

IC taps with control register and scan router coupling taps

Scan chain circuit supporting logic self test pattern injection dur...

Wafer with dio bidirectional lead, n dies, domains, clock leads

Test application time reduction using capture-per-cycle test points

Semiconductor apparatus and design apparatus

Combinatorial serial and parallel test access port selection in a J...

Electronic circuit having serial latch scan chains

Broadcast scan network

Test method and test apparatus for testing a plurality of blocks in...

Semiconductor device, electronic device, and self-diagnosis method...

Patents Applicationslast 30 patents

X-Masking for In-System Deterministic Test

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM

FLEXIBLE INTERFACE

CHIP TESTING CIRCUIT AND TESTING METHOD THEREOF

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

Microchip Having A Plurality Of Reconfigurable Test Structures

DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...

RAPID SCAN TESTING OF INTEGRATED CIRCUIT CHIPS

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

SCAN CHAIN OPERATIONS

DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

SCAN BASED TEST DESIGN IN SERDES APPLICATIONS

DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM

METHOD AND APPARATUS FOR DYNAMIC CONTROLLER BIST

MULTI-STAGE TEST RESPONSE COMPACTORS

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

INTEGRATED ELECTRONIC DEVICE HAVING A TEST ARCHITECTURE, AND TEST M...

SCAN TESTING SYSTEM, METHOD AND APPARATUS

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD...

DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM

Test Generation For Test-Per-Clock

Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology

CORE CIRCUIT TEST ARCHITECTURE

System and method for optimized board test and configuration