of parts of caches

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G06F12/0895

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0895of parts of caches

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Compression aware prefetch
- Patent number 12,242,384
- Issue date Mar 4, 2025
- Advanced Micro Devices, Inc.
- Pazhani Pillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory module
- Patent number 12,213,548
- Issue date Feb 4, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet cache system and method
- Patent number 12,216,587
- Issue date Feb 4, 2025
- Google LLC
- Jiazhen Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information processing system and memory system
- Patent number 12,210,458
- Issue date Jan 28, 2025
- Kioxia Corporation
- Tomoya Suzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flushing cache lines involving persistent memory
- Patent number 12,204,441
- Issue date Jan 21, 2025
- Altera Corporation
- Sharath Raghava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic processing device and arithmetic processing method
- Patent number 12,197,342
- Issue date Jan 14, 2025
- Fujitsu Limited
- Toru Hikichi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to cache key-value data in low-precision numer...
- Patent number 12,182,028
- Issue date Dec 31, 2024
- d-MATRIX CORPORATION
- Akhil Arunkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and micro-architecture support for decompression on core
- Patent number 12,182,018
- Issue date Dec 31, 2024
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for coupled cache management
- Patent number 12,164,434
- Issue date Dec 10, 2024
- Appian Corporation
- Brian Sullivan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 12,147,301
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performing caching in hashed storage
- Patent number 12,147,347
- Issue date Nov 19, 2024
- Samsung Electronics Co., Ltd.
- Chun-Chu Chen-Jhy Archie Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method for cleaning valid bits in cache memo...
- Patent number 12,147,350
- Issue date Nov 19, 2024
- Nuvoton Technology Corporation
- Yung-Chi Lan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible dictionary sharing for compressed caches
- Patent number 12,135,653
- Issue date Nov 5, 2024
- Advanced Micro Devices, Inc.
- Alexander D. Breslow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Saving track metadata format information for tracks demoted from ca...
- Patent number 12,135,655
- Issue date Nov 5, 2024
- International Business Machines Corporation
- Kyler A. Anderson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS
- Publication number 20250061062
- Publication date Feb 20, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...
- Publication number 20250053511
- Publication date Feb 13, 2025
- Next Silicon Ltd
- Dan SHECHTER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED SCRUBBING TRANSACTIONS
- Publication number 20250036522
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT
- Publication number 20250036571
- Publication date Jan 30, 2025
- BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACIÓN
- John D. DAVIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE ALLOCATION
- Publication number 20250028646
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Qirui Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CACHE LOADING AND VERIFICATION
- Publication number 20250028644
- Publication date Jan 23, 2025
- International Business Machines Corporation
- Yvo Thomas Bernard Mulder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM CACHE OPTIMIZATIONS FOR DEEP LEARNING COMPUTE ENGINES
- Publication number 20250028650
- Publication date Jan 23, 2025
- Intel Corporation
- Neta Zmora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS
- Publication number 20250013284
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCUMULATING A TAG CACHE FROM A PROFFERED DATASET
- Publication number 20240411698
- Publication date Dec 12, 2024
- Truist Bank
- Jonathan Randall Howarth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM CACHE TAG PROBING
- Publication number 20240394195
- Publication date Nov 28, 2024
- Rambus Inc.
- Steven C. WOO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE
- Publication number 20240354254
- Publication date Oct 24, 2024
- Lodestar Licensing Group LLC
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PROCESSING REQUEST FOR DATA STORED IN STACK AREA BY USING USE...
- Publication number 20240320159
- Publication date Sep 26, 2024
- Samsung Electronics Co., Ltd.
- Moongyung KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CACHE STRUCTURE FOR CACHING COMPRESSED AND UNCOMPRESSED DATA
- Publication number 20240320155
- Publication date Sep 26, 2024
- Imagination Technologies Limited
- Ross Martin Torkington
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING NON-CORRECTABLE ERRORS
- Publication number 20240311235
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER, METHOD OF DRIVING MEMORY CONTROLLER, AND MEMORY...
- Publication number 20240264946
- Publication date Aug 8, 2024
- SK HYNIX INC.
- Eun Soo JANG
- G06 - COMPUTING CALCULATING COUNTING

of parts of caches

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Compression aware prefetch

Data initialization techniques

Hybrid memory module

Packet cache system and method

Atomic compare and swap in a coherent cache system

Information processing system and memory system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Graphics processor data access and sharing

Flushing cache lines involving persistent memory

Methods and apparatus to reduce bank pressure using aggressive writ...

Hardware coherence signaling protocol

Arithmetic processing device and arithmetic processing method

Fully pipelined read-modify-write support

Method and apparatus to cache key-value data in low-precision numer...

Multi-tile memory management

Instruction and micro-architecture support for decompression on core

Methods and apparatus for allocation in a victim cache system

Systems and methods for coupled cache management

Cache structure and utilization

Methods and apparatus for read-modify-write support in multi-banked...

Parallelized scrubbing transactions

System and method for performing caching in hashed storage

Integrated circuit and method for cleaning valid bits in cache memo...

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Flexible dictionary sharing for compressed caches

Cache coherence shared state suppression

Saving track metadata format information for tracks demoted from ca...

Patents Applicationslast 30 patents

TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS

SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PARALLELIZED SCRUBBING TRANSACTIONS

METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

SYSTEMS AND METHODS FOR CACHE ALLOCATION

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

DYNAMIC CACHE LOADING AND VERIFICATION

SYSTEM CACHE OPTIMIZATIONS FOR DEEP LEARNING COMPUTE ENGINES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

CACHE COHERENCE SHARED STATE SUPPRESSION

STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE STRUCTURE AND UTILIZATION

ACCUMULATING A TAG CACHE FROM A PROFFERED DATASET

COMPRESSION TECHNIQUES

DRAM CACHE TAG PROBING

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

CACHE PROCESSING REQUEST FOR DATA STORED IN STACK AREA BY USING USE...

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

FLEXIBLE CACHE STRUCTURE FOR CACHING COMPRESSED AND UNCOMPRESSED DATA

HANDLING NON-CORRECTABLE ERRORS

VICTIM CACHE WITH WRITE MISS MERGING

MEMORY CONTROLLER, METHOD OF DRIVING MEMORY CONTROLLER, AND MEMORY...